公开(公告)号：US20240178154A1

公开(公告)日：2024-05-30

申请号：US18070708

申请日：2022-11-29

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen ,  Jaimal Mallory Williamson

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227

Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a molded package structure, where the multilevel package substrate has opposite first and second substrate sides, first and second conductive pads spaced apart from one another along the first substrate side, and a conductive substrate terminal that is exposed along the second substrate side and is electrically coupled to the second conductive pad. The semiconductor die is attached to the first substrate side and has opposite first and second die sides, and a die terminal along the first die side, the die terminal electrically coupled to the first conductive pad. The molded has a package side, a metal shield along the package side, and a conductive package via that extends through the molded package structure and electrically couples the metal shield to the second conductive pad.

公开(公告)号：US20240120297A1

公开(公告)日：2024-04-11

申请号：US17958254

申请日：2022-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jie Chen ,  Rajen Maricon Murugan ,  Chittranjan Mohan Gupta ,  Yiqi Tang

IPC: H01L23/66

CPC classification number: H01L23/66 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: An apparatus includes: a first conductor layer patterned into parallel strips having a first end and an opposite second end formed on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers extending through the dielectric material; a second conductor layer in the multilayer package substrate spaced from the first conductor layer, the second conductor layer patterned into parallel strips having a first end and a second end, the second conductor layer coupled to the first conductor layer by vertical connectors formed of the conductive vertical connection layers at the first end and the second end, and a semiconductor die mounted to the device side surface of the multilayer package substrate that is spaced from and coupled to the second conductor.

公开(公告)号：US20230317581A1

公开(公告)日：2023-10-05

申请号：US17710912

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Jie Chen ,  Chittranjan Mojan Gupta ,  Rajen Muricon Murugan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2924/15311 ,  H01L2224/16227 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204

Abstract: In a described example, an apparatus includes: a multilayer package substrate including a die mount area on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations on the die side surface for receiving power post connects and for receiving ground post connects for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.

公开(公告)号：US11735506B2

公开(公告)日：2023-08-22

申请号：US16206640

申请日：2018-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hung-Yu Chou ,  Bo-Hsun Pan ,  Yuh-Harng Chien ,  Fu-Hua Yu ,  Steven Alfred Kummerl ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503

Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

公开(公告)号：US20230021179A1

公开(公告)日：2023-01-19

申请号：US17379549

申请日：2021-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Chittranjan Mohan Gupta ,  Jie Chen

IPC: H01L49/02 ,  H01F17/00 ,  H05K3/46 ,  H05K1/11 ,  H02M3/158

Abstract: A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.

公开(公告)号：US11557722B2

公开(公告)日：2023-01-17

申请号：US17142539

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Ming Li ,  Yiqi Tang ,  Jie Chen ,  Enis Tuncer ,  Usman Mahmood Chaudhry ,  Tony Ray Larson ,  Rajen Manicon Murugan ,  John Paul Tellkamp ,  Satyendra Singh Chauhan

IPC: H01L43/14 ,  G01R33/07 ,  G01R15/20 ,  H01L43/06 ,  H01L23/495 ,  G01R33/00

Abstract: A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

公开(公告)号：US20250096189A1

公开(公告)日：2025-03-20

申请号：US18385694

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chen Chao ,  Bo Jiang ,  Wei Li ,  Jie Chen ,  Ruijie Huang ,  Liang Zheng ,  Qi Ming Bao ,  Bin Liu

IPC: H01L23/00 ,  B23K3/06

Abstract: An integrated circuit (IC) solder ball mounting apparatus comprises a ball storage unit for storing solder balls, a ball buffer unit configured to receive the solder balls from the ball storage unit in response to one or more pressure-actuated actions, and a gate valve configured to allow the solder balls to transfer to a ball mounting brush configured to place the solder balls onto area array contact structures formed on a wafer containing the integrated circuit.

公开(公告)号：US12211800B2

公开(公告)日：2025-01-28

申请号：US17500086

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US20240304517A1

公开(公告)日：2024-09-12

申请号：US18180024

申请日：2023-03-07

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Jie Chen ,  Yutaka Suzuki ,  Rajen Murugan

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/784 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/3737 ,  H01L21/565 ,  H01L21/784 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/165 ,  H01L2224/08235 ,  H01L2224/273 ,  H01L2224/29193 ,  H01L2224/32221 ,  H01L2224/94 ,  H01L2924/182

Abstract: An electronic device includes: a semiconductor die having opposite first and second sides and a conductive terminal along the first side; a conductive lead electrically coupled to the conductive terminal; a package structure that forms a top side of the electronic device and encloses a portion of the semiconductor die, the package structure including a first molding compound having a first thermal conductivity; and a thermally conductive layer on at least a portion of the second side of the semiconductor die, the thermally conductive layer including a second molding compound having a second thermal conductivity that is greater than the first thermal conductivity.

公开(公告)号：US11621232B2

公开(公告)日：2023-04-04

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.