公开(公告)号：US11587899B2

公开(公告)日：2023-02-21

申请号：US16941818

申请日：2020-07-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Naweed Anjum ,  Liang Wan ,  Michael Gerald Amaro

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/00 ,  H01L23/58 ,  H01L23/498 ,  H01L21/56

Abstract: A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

公开(公告)号：US20220209391A1

公开(公告)日：2022-06-30

申请号：US17138557

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Makarand Ramkrishna Kulkarni ,  Liang Wan ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01Q9/04 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01P3/08

Abstract: An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.

公开(公告)号：US20210327829A1

公开(公告)日：2021-10-21

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L33/62 ,  H01L23/00 ,  H01L33/00

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.

公开(公告)号：US12211800B2

公开(公告)日：2025-01-28

申请号：US17500086

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan ,  Makarand Ramkrishna Kulkarni ,  Jie Chen ,  Steven Alfred Kummerl

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

公开(公告)号：US11784114B2

公开(公告)日：2023-10-10

申请号：US17334491

申请日：2021-05-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Makarand Ramkrishna Kulkarni ,  Osvaldo Jorge Lopez ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Liang Wan

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49844 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16238

Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.

公开(公告)号：US11621232B2

公开(公告)日：2023-04-04

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US20220352087A1

公开(公告)日：2022-11-03

申请号：US17246115

申请日：2021-04-30

Applicant: Texas Instruments Incorporated

Inventor： Jie Chen ,  Yiqi Tang ,  Rajen Murugan ,  Liang Wan

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a multilayer package substrate including a first layer including a first dielectric and first metal layer including a first metal trace and a second layer including a second dielectric layer. An integrated circuit (IC) die includes bond pads, with a bottom side of the IC die attached to the first metal trace. Metal pillars are through the second dielectric layer connecting to the first metal trace. A third layer on the second layer includes a third dielectric layer on the second layer extending to a bottom side of the semiconductor package, and a second metal layer including second metal traces including inner second metal traces connected to the bond pads and outer second metal traces over the metal pillars, and filled vias providing externally accessible contact pads that connect the second metal traces to a bottom side of the semiconductor package.

公开(公告)号：US11362047B2

公开(公告)日：2022-06-14

申请号：US16850620

申请日：2020-04-16

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/495 ,  H01L23/00 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.