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公开(公告)号：US20240040268A1
公开(公告)日：2024-02-01
申请号：US18309055
申请日：2023-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Pandy Kalimuthu
CPC classification number: H04N23/85 , H04N23/843 , H04N23/11 , H04N25/131
Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.
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公开(公告)号：US11172172B2
公开(公告)日：2021-11-09
申请号：US15395001
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Shashank Dabral , Rajasekhar Allu , Niraj Nandan
Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.
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公开(公告)号：US20250168520A1
公开(公告)日：2025-05-22
申请号：US19027193
申请日：2025-01-17
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Manoj Koul , Pandy Kalimuthu , David Stoller
Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.
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公开(公告)号：US20250159365A1
公开(公告)日：2025-05-15
申请号：US19026992
申请日：2025-01-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Pandy Kalimuthu
IPC: H04N23/85 , H04N23/11 , H04N23/84 , H04N25/13 , H04N25/131
Abstract: Disclosed herein are improvements to pixel pattern conversion, upsampling, and IR decontamination processes. An example includes an image processing pipeline comprising an upstream component, a pattern conversion component downstream with respect to the upstream component in the image processing pipeline, and a downstream component relative to the pattern conversion component. The pattern conversion component is configured to obtain RGB-IR pixel data produced by the upstream component of the image processing pipeline and convert the RGB-IR pixel data into RGB pixel data and IR pixel data using a conversion engine. The conversion engine is configured to demosaic the RGB-IR pixel into the RGB pixel data and the IR pixel data, remosaic the RGB pixel data into an RGB pattern and the IR pixel data into an IR pattern and remove IR contamination from the RGB pixel data of the RGB pattern for use by the downstream component.
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Patent Agency Ranking
公开(公告)号：US12185007B2
公开(公告)日：2024-12-31
申请号：US18091798
申请日：2022-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Niraj Nandan , Mihir Narendra Mody , Rajasekhar Allu
IPC: H04N25/77 , H04N23/698 , H04N23/81
Abstract: In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.
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公开(公告)号：US20240040096A1
公开(公告)日：2024-02-01
申请号：US17983905
申请日：2022-11-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jing-Fei Ren , Hrushikesh Garud , Rajasekhar Allu , Gang Hua , Niraj Nandan , Mayank Mangla , Mihir Narendra Mody
CPC classification number: H04N9/646 , G06T7/90 , G06T7/0002 , G06T2207/10024 , G06T2207/30168
Abstract: Various embodiments disclosed herein relate to defective pixel detection and correction, and more specifically to using threshold functions based on color channels to compare pixel values to threshold values. A method is provided herein that comprises identifying a color channel of an image pixel in a frame and identifying a threshold function based at least on the color channel. The method further comprises applying the threshold function to one or more nearest-neighbor values to obtain a threshold value and determining whether a corresponding sensor pixel is defective based at least on a comparison of the image pixel to the threshold value.
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公开(公告)号：US20230388661A1
公开(公告)日：2023-11-30
申请号：US18194249
申请日：2023-03-31
Applicant: Texas Instruments Incorporated
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Manoj Koul , Pandy Kalimuthu , David Stoller
CPC classification number: H04N23/81 , H04N23/843 , H04N23/88
Abstract: In described examples, an integrated circuit includes first, second, third, and fourth image processing blocks, a data selection circuitry, and a pipeline memory. An input of the first image processing block receives raw image data. An input of the second image processing block is coupled to an output of the first image processing block. An input of the third image processing block is coupled to an output of the second image processing block. A first input of the data selection circuitry is coupled to an output of the first image processing block, and a second input of the data selection circuitry is coupled to an output of the second image processing block. A data input of the pipeline memory is coupled to an output of the data selection circuitry, and an output of the pipeline memory is coupled to an input of the fourth image processing block.
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公开(公告)号：US20230385102A1
公开(公告)日：2023-11-30
申请号：US18175364
申请日：2023-02-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Niraj Nandan , Mihir Mody , Rajasekhar Allu , Pandy Kalimuthu
CPC classification number: G06F9/4881 , G06F9/30189 , G06F9/30079
Abstract: Various embodiments disclosed herein relate to hardware enabled pipeline control. In a hardware acceleration system, pipelines are configured to include a hardware enable flag that allows hardware initiation of the pipeline based on triggering of a configurable event. The pipeline can be configured to set the event that triggers the initiation of the pipeline. For example, the end of pipeline of a first pipeline may trigger the initiation of a second pipeline. Accordingly, pipelines that are configured to allow hardware enable based on a specifically configured event are not subject to the extra processing required to initiate the pipeline via software in external memory and triggered by an external controller.
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公开(公告)号：US11770624B2
公开(公告)日：2023-09-26
申请号：US18072813
申请日：2022-12-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Shashank Dabral , Rajasekhar Allu , Niraj Nandan
CPC classification number: H04N23/843 , G06T1/20 , H04N9/67 , H04N2209/046
Abstract: An image signal processor includes a first matrix processing circuit, a post processing circuit, a second matrix processing circuit, and a split visual and analytics circuit. The first matrix processing circuit is configured to receive a plurality of component images generated based on an image captured by an image sensor and generate a plurality of first matrix outputs based on the plurality of component images. The post processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a first luminance component of the image and a chrominance component of the image. The second matrix processing circuit is configured to perform color conversion on the plurality of first matrix outputs to generate a second luminance component of the image and a saturation component of the image. The split visual and analytics circuit is configured to generate visual and analytic data of the image.
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