公开(公告)号：US20220359976A1

公开(公告)日：2022-11-10

申请号：US17566067

申请日：2021-12-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Herbsommer

IPC: H01Q1/22 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01Q19/10 ,  H01Q9/04

Abstract: In a described example, an apparatus includes: a patch antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna.

公开(公告)号：US20220344796A1

公开(公告)日：2022-10-27

申请号：US17539110

申请日：2021-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Juan Alejandro Herbsommer

IPC: H01Q1/22 ,  H01L23/31 ,  H01L23/66 ,  H05K1/02

Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.

公开(公告)号：US10475786B1

公开(公告)日：2019-11-12

申请号：US16037695

申请日：2018-07-17

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Makarand Ramkrishna Kulkarni

IPC: H01L49/02 ,  H03F3/19 ,  H01L27/07 ,  H01L23/31 ,  H05K1/02 ,  H01L23/00 ,  H01L23/522

Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.

公开(公告)号：US20170347490A1

公开(公告)日：2017-11-30

申请号：US15162888

申请日：2016-05-24

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland GmbH

Inventor： Matthew David Romig ,  Robert Clair Keller ,  Ming Li ,  Yiqi Tang

IPC: H05K7/20 ,  H05K1/02 ,  H05K13/00

CPC classification number: H05K7/20418 ,  H01Q1/02 ,  H01Q1/2283 ,  H01Q21/061 ,  H05K1/0204 ,  H05K7/20509 ,  H05K13/00 ,  H05K2201/066

Abstract: A heat dissipating antenna comprised of a low-attenuating heat spreader bonded to a high frequency antenna or antenna array.An integrated circuit with a wireless integrated circuit chip, and a heat dissipating antenna coupled to the wireless integrated circuit chip. A method of forming a heat dissipating antenna.

公开(公告)号：US12243911B2

公开(公告)日：2025-03-04

申请号：US17017642

申请日：2020-09-10

Applicant: Texas Instruments Incorporated

Inventor： Matthew David Romig ,  Enis Tuncer ,  Rajen Manicon Murugan ,  Yiqi Tang

IPC: H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: In described examples of an isolation device, an isolation die that has a set of bond pads is mounted on a first lead frame that has a set of leads. A portion of the bond pads are coupled to respective leads. A first mold material encapsulates the isolation device and the first lead frame forming a first package. The first package is mounted on a second lead frame that has a set of leads. A portion of the first lead frame leads is coupled to respective ones of the second lead frame leads. A second mold material encapsulates the first package and the second lead frame.

公开(公告)号：US12243849B2

公开(公告)日：2025-03-04

申请号：US17491378

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chittranjan Mohan Gupta ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Jie Chen ,  Tianyi Luo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

公开(公告)号：US12224480B2

公开(公告)日：2025-02-11

申请号：US17736653

申请日：2022-05-04

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen Manicon Murugan

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q9/04 ,  H01Q13/02 ,  H01Q19/10

Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.

公开(公告)号：US20240258704A1

公开(公告)日：2024-08-01

申请号：US18104124

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Murugan ,  Harshpreet Bakshi

IPC: H01Q13/00 ,  H01Q1/48 ,  H01Q9/04

CPC classification number: H01Q13/00 ,  H01Q1/48 ,  H01Q9/0407

Abstract: A microelectronic package includes a waveguide radiation receiver formed in a first conductor layer of a multilayer package substrate, the multilayer package substrate comprising the first conductor layer spaced from a second conductor layer by a dielectric layer. The microelectronic package further includes a tubular waveguide mounted to the multilayer package substrate such that a central aperture of the tubular waveguide is over the waveguide radiation receiver, and a feed line coupling the waveguide radiation receiver to a transmitter-receiver, the feed line including a conductive via traversing the dielectric layer electrically coupling a first portion of the feed line in the first conductor layer to a second portion of the feed line in the second conductor layer, the first portion adjacent the waveguide radiation receiver, and the second portion adjacent the transmitter-receiver.

公开(公告)号：US20240178163A1

公开(公告)日：2024-05-30

申请号：US18072026

申请日：2022-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Rajen M. Murugan ,  Aditya Nitin Jogalekar

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/06 ,  H01L23/31 ,  H01Q5/25 ,  H01Q9/28 ,  H01Q13/10

CPC classification number: H01L23/66 ,  H01L23/06 ,  H01L23/3107 ,  H01L24/20 ,  H01Q5/25 ,  H01Q9/285 ,  H01Q13/106 ,  H01L2223/6677 ,  H01L2224/221

Abstract: An example semiconductor package comprises a semiconductor die having a top surface, a passivation layer over the top surface, a first metal layer on the first passivation layer, an antenna formed in the first metal layer and offset from the semiconductor die, the antenna having a slot bow-tie configuration, a transmission line formed in the first metal layer, the transmission line coupling the semiconductor die to the antenna, and an insulating material separating the first metal layer from a second metal layer, the second metal layer configured to function as a ground reflector for the antenna. The second metal layer may extend below the antenna and the semiconductor die.

公开(公告)号：US11978709B2

公开(公告)日：2024-05-07

申请号：US17752037

申请日：2022-05-24

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Yiqi Tang ,  Christopher Daniel Manack ,  Rajen Manicon Murugan ,  Liang Wan ,  Hiep Xuan Nguyen

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/495 ,  H01L33/00 ,  H01L33/62 ,  H01L21/683 ,  H01L25/16

CPC classification number: H01L23/60 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/28 ,  H01L24/82 ,  H01L33/005 ,  H01L33/62 ,  H01L21/6835 ,  H01L24/24 ,  H01L24/25 ,  H01L25/167 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A system in a package (SIP) includes carrier layer regions that have a dielectric material with a metal post therethrough, where adjacent carrier layer regions define a gap. A driver IC die is positioned in the gap having nodes connected to bond pads exposed by openings in a top side of a first passivation layer, with the bond pads facing up. A dielectric layer is on the first passivation layer and carrier layer region that includes filled through vias coupled to the bond pads and to the metal post. A light blocking layer is on sidewalls and a bottom of the substrate. A first device includes a light emitter that has first bondable features. The light blocking layer can block at least 90% of incident light. The first bondable features are flipchip mounted to a first portion of the bond pads.