Abstract:
A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer.
Abstract:
A thin film transistor and a method of manufacturing the same are provided. The thin film transistor includes a substrate; a buffer layer formed on the substrate; a source and a drain spaced apart from each other on the buffer layer; a channel layer formed on the buffer layer to connect the source and the drain with each other; and a gate formed on the buffer layer to be spaced apart from the source, the drain and the channel layer.
Abstract:
A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of the channel region, and offset regions, each offset regions disposed between the channel region and one of the source and drain regions at both sides of the channel region, a gate insulating layer covering the channel region and the offset regions disposed at both sides of the channel region excluding the source and drain regions, and a gate layer formed on the channel region excluding the offset regions. The thin film transistor has the structure in which an offset or LDD is obtained without an additional mask process.
Abstract:
The invention provides water-based one package coat comprising acrylic resin having specific long chain primary hydroxyl-containing side chains as crosslinking functional groups and a solubility parameter of 9.30-11.20, and blocked polyisocyanate compound having a solubility parameter of 9.00-11.50, the difference ΔSP between the solubility parameter (SP1) of the acrylic resin and the solubility parameter (SP2) of the blocked polyisocyanate compound (ΔSP=(SP1)−(SP2)) being within a range of from −0.80 to 1.50.
Abstract:
Provided is an organic light emitting display, in which a semiconductor circuit unit of 2T-1C structure including a switching transistor and a driving transistor formed of single crystalline silicon is formed on a plastic substrate. A method of fabricating the single crystalline silicon includes: growing a single crystalline silicon layer to a predetermined thickness on a crystal growth plate; depositing a buffer layer on the single crystalline silicon layer; forming a partition layer at a predetermined depth in the single crystalline silicon layer by, e.g., implanting hydrogen ions in the single crystalline silicon layer from an upper portion of an insulating layer; attaching a substrate to the buffer layer; and releasing the partition layer of the single crystalline silicon layer by heating the partition layer from the crystal growth plate to obtain a single crystalline silicon layer of a predetermined thickness on the substrate.
Abstract:
A method for forming a Field Effect Transistor (FET) within a strain effect semiconductor layer is disclosed, whereby the source and drain of the FET are formed only in the strain effect silicon layer. The FET may be formed as a gate electrode of a p-channel type field effect transistor, and a gate electrode of a n-channel type field effect transistor on the silicon layer which has the strain effect through a gate insulating film. The sources and drains of p- and n-type diffusion layers are then formed in the silicon layer having the strain effect, on both sides of the gate electrode.
Abstract:
A fabricating method for a semiconductor device includes forming a heat spreading material on rear surface of the semiconductor wafer. The semiconductor wafer has a plurality of device areas and scribe lines which are arranged between the device areas. After the heat spreading material is formed on rear surface of the semiconductor wafer, the semiconductor wafer is separated at the scribe lines.
Abstract:
A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer.
Abstract:
A processing device has a personal authentication information receiving unit for receiving personal authentication information, a security information DB, and a processing information managing unit. The processing information managing unit converts the personal authentication information received by the personal authentication receiving unit to a user ID, detects an event concerning a processing operation, and associates the event with the user ID, thereby creating or updating an access management table for processing performance information, for storage in the security information DB. The processing information management unit then controls access to the processing performance information based on the access management table and the user ID obtained by conversion of the personal authentication information received by the personal authentication information receiving unit.
Abstract:
In a method of forming a polysilicon film, a thin film transistor including a polysilicon film, and a method of manufacturing a thin film transistor including a polysilicon film, the thin film transistor includes a substrate, a first heat conduction film on the substrate, a second heat conduction film adjacent to the first heat conduction film, the second heat conduction film having a lower thermal conductivity than the first heat conduction film, a polysilicon film on the second heat conduction film and the first heat conduction film adjacent to the second heat conduction film, and a gate stack on the polysilicon film. The second heat conduction film may either be on the first heat conduction film or, alternatively, the first heat conduction film may be non-contiguous and the second heat conduction film may be interposed between portions of the non-contiguous first heat conduction film.