公开(公告)号：US11444095B2

公开(公告)日：2022-09-13

申请号：US17229848

申请日：2021-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L29/76 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11568 ,  H01L27/11573 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/311

Abstract: A semiconductor device with integrated memory devices and metal-oxide-semiconductor (MOS) devices, including a substrate with a first area and a second area, multiple double-diffused metal-oxide-semiconductor (DMOS) devices on the first area, wherein the double-diffused metal-oxide-semiconductor (DMOS) device includes a field oxide on the substrate, a first gate dielectric layer adjacent to the field oxide, and a first polysilicon gate on the field oxide and the first gate dielectric layer, and multiple memory units on the second area, wherein the memory unit includes an oxide-nitride-oxide (ONO) tri-layer and a second polysilicon gate on the oxide-nitride-oxide (ONO) tri-layer, wherein a top surface of the second polysilicon gate of the memory unit in the second area and a top surface of the first polysilicon gate of the double-diffused metal-oxide-semiconductor (DMOS) in the first area are on the same level.

公开(公告)号：US20210119004A1

公开(公告)日：2021-04-22

申请号：US17134131

申请日：2020-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/792

Abstract: A memory device includes a main cell on a substrate, a first reference cell adjacent to one side of the main cell, and a second reference cell adjacent to another side of the main cell. Preferably, the main cell includes a first gate electrode on the substrate, a second gate electrode on one side of the first gate electrode and covering a top surface of the first gate electrode, a first charge trapping layer between the first gate electrode and the second gate electrode and including a first oxide-nitride-oxide (ONO) layer, a third gate electrode on another side of the first gate electrode and covering the top surface of the first gate electrode, and a second charge trapping layer between the first gate electrode and the third gate electrode and including a second ONO layer.

公开(公告)号：US10903326B2

公开(公告)日：2021-01-26

申请号：US16246538

申请日：2019-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

公开(公告)号：US20200227531A1

公开(公告)日：2020-07-16

申请号：US16246538

申请日：2019-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Sung Huang ,  Shen-De Wang ,  Chia-Ching Hsu ,  Wang Xiang

IPC: H01L29/423 ,  H01L29/792 ,  H01L29/40

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; forming a second gate structure on the substrate and on one side of the first gate structure; forming a third gate structure on the substrate and on another side of the first gate structure; forming source/drain regions adjacent to the second gate structure and the third gate structure; and forming contact plugs to contact the first gate structure, the second gate structure, the third gate structure, and the source/drain regions.

公开(公告)号：US09978762B2

公开(公告)日：2018-05-22

申请号：US15487419

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/11531 ,  H01L27/11529 ,  H01L27/11573

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

公开(公告)号：US20240397838A1

公开(公告)日：2024-11-28

申请号：US18795158

申请日：2024-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10N70/00 ,  H10N70/20

Abstract: A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.

公开(公告)号：US12156487B2

公开(公告)日：2024-11-26

申请号：US18382055

申请日：2023-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H10N70/00 ,  H10B63/00

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming the RRAM device.

公开(公告)号：US20240260489A1

公开(公告)日：2024-08-01

申请号：US18635027

申请日：2024-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8265 ,  H10N70/021 ,  H10N70/245 ,  H10N70/841 ,  H10N70/8833

Abstract: A semiconductor memory device includes a substrate, a first dielectric layer on the substrate, a bottom electrode on the first dielectric layer, a second dielectric layer on the first dielectric layer, and a top electrode in the second dielectric layer. The top electrode has a lower portion around the bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrode and around the tapered upper portion of the top electrode. A resistive-switching layer is disposed between a sidewall of the bottom electrode and a sidewall of the lower portion of the top electrode and between the third dielectric layer and a sidewall of the tapered upper portion of the top electrode. An air gap is disposed in the third dielectric layer.

公开(公告)号：US20240215251A1

公开(公告)日：2024-06-27

申请号：US18602040

申请日：2024-03-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu

IPC: H10B43/35 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H10B43/35 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate disposed on a substrate, a dielectric layer and two charge trapping layers, wherein the dielectric layer is disposed between the substrate and the memory gate, and the two charge trapping layers are disposed at two opposite sides of the memory gate, wherein each of the charge trapping layers comprises an L-shape cross-sectional profile, and two selective gates disposed on the substrate, thereby constituting a two bit memory cell, wherein a top surface of each selective gate is higher than a top surface of the memory gate.

公开(公告)号：US12010931B2

公开(公告)日：2024-06-11

申请号：US17196979

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Wang Xiang ,  Shen-De Wang

IPC: H01L45/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/841 ,  H10B63/845 ,  H10N70/021 ,  H10N70/066 ,  H10N70/8833

Abstract: A RRAM (resistive random-access memory) device includes a bottom electrode line, a top electrode island and a resistive material. The bottom electrode line is directly on a first metal structure. The top electrode island is disposed beside the bottom electrode line. The resistive material is sandwiched by a sidewall of the bottom electrode line and a sidewall of the top electrode island. The present invention also provides a method of forming said RRAM device.