公开(公告)号：US20180350673A1

公开(公告)日：2018-12-06

申请号：US15927106

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Wei-Hsin Liu

IPC: H01L21/768 ,  H01L21/324 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

公开(公告)号：US20180301458A1

公开(公告)日：2018-10-18

申请号：US15922899

申请日：2018-03-15

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Chung-Yen Feng

IPC: H01L27/108 ,  H01L23/532 ,  H01L23/522 ,  H01L21/285 ,  H01L23/528 ,  H01L21/768

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

公开(公告)号：US09754943B1

公开(公告)日：2017-09-05

申请号：US15272425

申请日：2016-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Wei-Hsin Liu ,  Jui-Min Lee ,  Chia-Lung Chang

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/10808 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/53295 ,  H01L27/10823 ,  H01L27/10876

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural word lines and plural bit lines. The word lines are disposed in the substrate along a first trench extending along a first direction. Each of the word lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes TiSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof. The bit lines are disposed over the word lines and extended along a second direction across the first direction.

公开(公告)号：US11799012B2

公开(公告)日：2023-10-24

申请号：US17012088

申请日：2020-09-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/423 ,  H10B12/00 ,  H01L21/285

CPC classification number: H01L29/4941 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/3213 ,  H01L29/42372 ,  H10B12/05 ,  H10B12/482 ,  H01L21/28518 ,  H01L21/28556 ,  H10B12/30

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20220130839A1

公开(公告)日：2022-04-28

申请号：US17570345

申请日：2022-01-06

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Chia-Chen Wu ,  Kai-Jiun Chang ,  Yi-An Huang ,  Tsun-Min Cheng

IPC: H01L27/108

Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

公开(公告)号：US11088023B2

公开(公告)日：2021-08-10

申请号：US15927106

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Wei-Hsin Liu

IPC: H01L21/768 ,  H01L21/324 ,  H01L27/108 ,  H01L23/532 ,  H01L21/285

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

公开(公告)号：US10475900B2

公开(公告)日：2019-11-12

申请号：US15869005

申请日：2018-01-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Jui-Min Lee ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Wei-Hsin Liu

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/66 ,  H01L27/108 ,  H01L21/28

Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C.-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.

公开(公告)号：US20190319107A1

公开(公告)日：2019-10-17

申请号：US15985730

申请日：2018-05-22

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chun-Chieh Chiu ,  Pin-Hong Chen ,  Yi-Wei Chen ,  Tsun-Min Cheng ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chih-Chieh Tsai ,  Kai-Jiun Chang ,  Yi-An Huang ,  Chia-Chen Wu ,  Tzu-Hao Liu

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/28 ,  H01L29/423 ,  H01L27/108

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

公开(公告)号：US20190027479A1

公开(公告)日：2019-01-24

申请号：US15990837

申请日：2018-05-29

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Chen Wu ,  Yi-Wei Chen ,  Chi-Mao Hsu ,  Kai-Jiun Chang ,  Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tsun-Min Cheng ,  Yi-An Huang

IPC: H01L27/108 ,  C23C14/06 ,  C23C14/58 ,  C23C14/34

Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.

公开(公告)号：US20180212034A1

公开(公告)日：2018-07-26

申请号：US15869005

申请日：2018-01-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Kai-Jiun Chang ,  Tsun-Min Cheng ,  Chih-Chieh Tsai ,  Jui-Min Lee ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Wei-Hsin Liu

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/285 ,  H01L27/108

Abstract: A method for manufacturing a semiconductor device with a cobalt silicide film is provided in the present invention. The method includes the steps of providing a silicon structure with an interlayer dielectric formed thereon, forming a contact hole in the interlayer dielectric to expose the silicon structure, depositing a cobalt film on the exposed silicon structure at a temperature between 300° C-400° C., wherein a cobalt protecting film is in-situ formed on the surface of the cobalt film, performing a rapid thermal process to transform the cobalt film into a cobalt silicide film, and removing untransformed cobalt film.