公开(公告)号：US20190006528A1

公开(公告)日：2019-01-03

申请号：US15660982

申请日：2017-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Ching-Chung Yang

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.

公开(公告)号：US20180197742A1

公开(公告)日：2018-07-12

申请号：US15402970

申请日：2017-01-10

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/265 ,  H01L21/266

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/1095

Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.

公开(公告)号：US09922881B2

公开(公告)日：2018-03-20

申请号：US14993623

申请日：2016-01-12

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/7836

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US20180047809A1

公开(公告)日：2018-02-15

申请号：US15234432

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/08 ,  H01L21/266 ,  H01L29/732 ,  H01L29/10

CPC classification number: H01L29/1004 ,  H01L29/0653 ,  H01L29/0813 ,  H01L29/66272 ,  H01L29/732

Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.

公开(公告)号：US20230253481A1

公开(公告)日：2023-08-10

申请号：US17688836

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761

CPC classification number: H01L29/66681 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761

Abstract: A fabricating method of a high voltage transistor includes providing a high voltage transistor. The high voltage transistor includes a substrate. A gate structure is disposed on the substrate. A source drift region and a drain drift region are respectively disposed at two sides of the gate structure and embedded within the substrate. A source is disposed in the source drift region. A drain is disposed within the drain drift region. The steps of fabricating the drain drift region include defining a drain drift region predetermined region on the substrate by using a photo mask. The photo mask includes a first comb-liked pattern. The first comb-liked pattern includes a first rectangle and numerous first tooth structures. Then, an ion implantation process is performed to implant dopants into the drain drift region predetermined region. Then, dopants in the drain drift region predetermined region are diffused to form the drain drift region.

公开(公告)号：US20180158738A1

公开(公告)日：2018-06-07

申请号：US15886717

申请日：2018-02-01

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L27/092

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US09947746B2

公开(公告)日：2018-04-17

申请号：US15234432

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L21/266 ,  H01L29/732

CPC classification number: H01L29/1004 ,  H01L29/0653 ,  H01L29/0813 ,  H01L29/66272 ,  H01L29/732

Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.

公开(公告)号：US09741850B1

公开(公告)日：2017-08-22

申请号：US15235320

申请日：2016-08-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Ping-Hung Chiang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang ,  Kuan-Liang Liu ,  Kai-Kuen Chang

IPC: H01L29/745 ,  H01L29/76 ,  H01L23/58 ,  H01L21/00 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/1087 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/7834

Abstract: A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric layer is disposed below said gate electrode and protrudes therefrom to said drain, thereby separating said gate electrode and said drain by a substantial distance to reduce gate induced drain leakage.

公开(公告)号：US09653343B1

公开(公告)日：2017-05-16

申请号：US15172136

申请日：2016-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao ,  Chang-Po Hsiung

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/76235 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42364

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

公开(公告)号：US09391196B1

公开(公告)日：2016-07-12

申请号：US14805474

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor device and a manufacturing method thereof are provided. The HV MOS transistor device includes a semiconductor substrate, a gate structure, a first sub-gate structure, and a drain region. The gate structure is disposed on the semiconductor substrate. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the semiconductor substrate, the first sub-gate structure is separated from the gate structure, and the first sub-gate structure is disposed on the first region of the semiconductor substrate. The drain region is disposed in the first region of the semiconductor substrate. The drain region is electrically connected to the first sub-gate structure via a first contact structure disposed on the drain region and the first sub-gate structure.

Abstract translation: 提供高压金属氧化物半导体（HV MOS）晶体管器件及其制造方法。 HV MOS晶体管器件包括半导体衬底，栅极结构，第一子栅极结构和漏极区域。 栅极结构设置在半导体衬底上。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底上，第一子栅极结构与栅极结构分离，第一子栅极结构设置在半导体衬底的第一区域上。 漏极区域设置在半导体衬底的第一区域中。 漏极区域经由设置在漏极区域和第一子栅极结构上的第一接触结构电连接到第一子栅极结构。