公开(公告)号：US11139384B2

公开(公告)日：2021-10-05

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/43 ,  H01L29/51 ,  H01L29/40 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US20200006514A1

公开(公告)日：2020-01-02

申请号：US16561002

申请日：2019-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Yun-Tzu Chang ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Shih-Min Chou ,  Yang-Ju Lu ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Kuan-Chun Lin ,  Chi-Mao Hsu

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/49

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.

公开(公告)号：US10199228B2

公开(公告)日：2019-02-05

申请号：US15479292

申请日：2017-04-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L21/76 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.

公开(公告)号：US09691704B1

公开(公告)日：2017-06-27

申请号：US15175299

申请日：2016-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia-Chang Hsu ,  Nien-Ting Ho ,  Ching-Yun Chang ,  Yen-Chen Chen ,  Shih-Min Chou ,  Yun-Tzu Chang ,  Yang-Ju Lu ,  Wei-Ming Hsiao ,  Wei-Ning Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.

公开(公告)号：US20150061042A1

公开(公告)日：2015-03-05

申请号：US14016234

申请日：2013-09-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsun-Min Cheng ,  Nien-Ting Ho ,  Chien-Hao Chen ,  Ching-Yun Chang ,  Hsin-Fu Huang ,  Min-Chuan Tsai ,  Chi-Yuan Sun ,  Chi-Mao Hsu

IPC: H01L29/49 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/285

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.

Abstract translation: 提供了金属栅极结构。 金属栅极结构包括半导体衬底，栅极电介质层，多层P型功函数层和导电金属层。 栅极电介质层设置在半导体衬底上。 多层P型功函数层设置在栅极电介质层上，多层P型功函数层至少包含结晶P型功函数层和至少一非晶P型功函数层 层。 此外，导电性金属层设置在多层P型功函数层上。

公开(公告)号：US20140248762A1

公开(公告)日：2014-09-04

申请号：US14277812

申请日：2014-05-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Chia Chang Hsu ,  Nien-Ting Ho ,  Bor-Shyang Liao ,  Shu Min Huang ,  Min-Chung Cheng ,  Yu-Ru Yang

IPC: H01L21/768

CPC classification number: H01L21/76889 ,  H01L29/41791 ,  H01L29/66795

Abstract: A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed.

Abstract translation: 半导体器件的制造方法包括以下步骤。 首先，提供基板，在基板上形成至少一个翅片结构，然后在翅片结构上沉积金属层以形成自对准硅化物层。 在沉积金属层之后，除去金属层，但在除去金属层之前不进行RTP。 然后在去除金属层之后执行RTP。

公开(公告)号：US11538917B2

公开(公告)日：2022-12-27

申请号：US17353830

申请日：2021-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.

公开(公告)号：US11424408B2

公开(公告)日：2022-08-23

申请号：US17384817

申请日：2021-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L21/02 ,  H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US20210057643A1

公开(公告)日：2021-02-25

申请号：US16576784

申请日：2019-09-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Min Chou ,  Kuo-Chih Lai ,  Wei-Ming Hsiao ,  Hui-Ting Lin ,  Szu-Yao Yu ,  Nien-Ting Ho ,  Hsin-Fu Huang ,  Chin-Fu Lin

IPC: H01L45/00

Abstract: An ReRAM structure includes a dielectric layer. A first ReRAM and a second ReRAM are disposed on the dielectric layer. The second ReRAM is at one side of the first ReRAM. A trench is disposed in the dielectric layer between the first ReRAM and the second ReRAM. The first ReRAM includes a bottom electrode, a variable resistive layer and a top electrode. The variable resistive layer is between the bottom electrode and the top electrode. A width of the bottom electrode is smaller than a width of the top electrode. The width of the bottom electrode is smaller than a width of the variable resistive layer.

公开(公告)号：US10734496B2

公开(公告)日：2020-08-04

申请号：US16177368

申请日：2018-10-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first bottom barrier metal (BBM) layer on the first region and the second region; forming a first work function metal layer on the first BBM layer on the first region and the second region; removing the first work function metal (WFM) layer and part of the first BBM layer on the second region; and forming a diffusion barrier layer on the first WFM layer on the first region and the first BBM layer on the second region.