公开(公告)号：US20230231021A1

公开(公告)日：2023-07-20

申请号：US17669381

申请日：2022-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/40 ,  H01L29/778 ,  H01L21/3115 ,  H01L29/66

CPC classification number: H01L29/408 ,  H01L21/31155 ,  H01L29/7786 ,  H01L29/66462

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a first layer having a negative charge region adjacent to one side of the p-type semiconductor layer, and then forming a second layer having a positive charge region adjacent to another side of the p-type semiconductor layer.

公开(公告)号：US20220310824A1

公开(公告)日：2022-09-29

申请号：US17333045

申请日：2021-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A method for forming a HEMT is disclosed. A substrate is provided. A buffer layer, a channel layer on the buffer layer, a barrier layer on the channel layer, and a semiconductor gate layer on the barrier layer are formed on the substrate. A metal gate layer is formed on the semiconductor gate layer. A spacer is formed on sidewalls of the metal gate layer. The semiconductor gate layer is then etched by using the spacer and the metal gate layer as an etching mask. A passivation layer is then formed to cover the barrier layer, the semiconductor gate layer and the metal gate layer. An opening is formed in the passivation layer to expose the metal gate layer. A gate electrode is formed on the passivation layer and in direct contact with the metal gate layer.

公开(公告)号：US20220190149A1

公开(公告)日：2022-06-16

申请号：US17152742

申请日：2021-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A third III-V compound layer is disposed on the second III-V compound layer. The first III-V compound layer and the third III-V compound layer are composed of the same group III-V elements. The third III-V compound layer includes a body and numerous finger parts. Each of the finger parts is connected to the body. All finger parts are parallel to each other and do not contact each other. A source electrode, a drain electrode and a gate electrode are disposed on the first III-V compound layer.

公开(公告)号：US20220123118A1

公开(公告)日：2022-04-21

申请号：US17073410

申请日：2020-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/792

Abstract: A semiconductor structure includes a substrate, an insulating layer disposed on the substrate, an active layer disposed on the insulating layer, a first semiconductor device formed in a first device region of the active layer, a charge trap structure through the active layer and surrounding the first device region, and a charge trap layer between the insulating layer and the substrate and extending laterally to underlie the first device region and the charge trap structure.

公开(公告)号：US11289382B2

公开(公告)日：2022-03-29

申请号：US17121767

申请日：2020-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/306 ,  H01L21/3065

Abstract: A method of forming a semiconductor structure. A first sacrificial gate is formed on a substrate. A spacer is formed on a sidewall of the first sacrificial gate. In the substrate, adjacent to the first sacrificial gate, a source region and a drain region are formed. A channel region is formed between the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed on the channel region between the spacers. The substrate is etched via the gate trench, thereby forming a recessed trench between the source region and the drain region, and extending into the substrate. The recessed trench has a hexagonal cross-sectional profile. A stress inducing material layer is then formed in the recessed trench. A channel layer is epitaxially grown on the stress inducing material layer. A gate structure is formed on the channel layer.

公开(公告)号：US20220013718A1

公开(公告)日：2022-01-13

申请号：US17483790

申请日：2021-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L45/00 ,  H01L27/24

Abstract: A multi-bit resistive random access memory cell includes a plurality of bottom electrodes, a plurality of dielectric layers, a top electrode and a resistance layer. The bottom electrodes and the dielectric layers are interleaved layers, each of the bottom electrodes is sandwiched by the dielectric layers, and a through hole penetrates through the interleaved layers. The top electrode is disposed in the through hole. The resistance layer is disposed on a sidewall of the through hole and is between the top electrode and the interleaved layers, thereby the top electrode, the resistance layer and the bottom electrodes constituting a multi-bit resistive random access memory cell. The present invention also provides a method of forming the multi-bit resistive random access memory cell.

公开(公告)号：US20210143067A1

公开(公告)日：2021-05-13

申请号：US17121767

申请日：2020-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method of forming a semiconductor structure. A first sacrificial gate is formed on a substrate. A spacer is formed on a sidewall of the first sacrificial gate. In the substrate, adjacent to the first sacrificial gate, a source region and a drain region are formed. A channel region is formed between the source region and the drain region. The first sacrificial gate is removed, and a gate trench is formed on the channel region between the spacers. The substrate is etched via the gate trench, thereby forming a recessed trench between the source region and the drain region, and extending into the substrate. The recessed trench has a hexagonal cross-sectional profile. A stress inducing material layer is then formed in the recessed trench. A channel layer is epitaxially grown on the stress inducing material layer. A gate structure is formed on the channel layer.

公开(公告)号：US20210134747A1

公开(公告)日：2021-05-06

申请号：US16675200

申请日：2019-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L23/00 ,  H01L25/065

Abstract: A semiconductor structure is disclosed, including a substrate, an insulating layer on the substrate, a barrier layer on the insulating layer, a bonding dielectric layer on the barrier layer, and a bonding pad extending through the insulating layer, the barrier layer and the bonding dielectric layer. A top surface of the bonding pad exposed from the bonding dielectric layer for bonding to another bonding pad on another substrate. A liner on a bottom surface of the bonding pad directly contacts the substrate.

公开(公告)号：US09865707B2

公开(公告)日：2018-01-09

申请号：US14813127

申请日：2015-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/324 ,  H01L21/31 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02636 ,  H01L21/265 ,  H01L21/31 ,  H01L21/324 ,  H01L21/823821 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7848

Abstract: A fabricating method of a strained FET includes providing a semiconductive layer having a gate structure disposed thereon, wherein an epitaxial layer is embedded in the semiconductive layer aside the gate structure. Later, an element supply layer is formed to contact the epitaxial layer, wherein the element supply layer and the epitaxial layer have at least one identical element besides silicon. Finally, a thermal process is performed to drive the element into the epitaxial layer.

公开(公告)号：US20250040172A1

公开(公告)日：2025-01-30

申请号：US18915372

申请日：2024-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Hsun-Wen Wang

IPC: H01L29/778 ,  H01L29/06 ,  H01L29/66

Abstract: A method for forming a high electron mobility transistor includes the steps of forming an epitaxial stack on a substrate; forming a gate structure on the epitaxial stack, wherein the gate structure comprises a semiconductor gate layer, a metal gate layer on the semiconductor gate layer, and a spacer on a top surface of the semiconductor gate layer and a sidewall of the metal gate layer; forming a passivation layer covering the epitaxial stack and the gate structure; forming an opening through the passivation layer on the gate structure to expose a portion of the spacer; and removing the spacer through the opening to form an air gap between the sidewall of metal gate layer, the top surface of the semiconductor gate layer and a sidewall of the passivation layer.