中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

43 records (took 0.016 seconds)

    METHOD OF FORMING TRENCHES
    12.
    发明申请
    METHOD OF FORMING TRENCHES 有权
    形成倾角的方法

    公开(公告)号：US20160203982A1

    公开(公告)日：2016-07-14

    申请号：US14636200

    申请日：2015-03-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chao-Hung Lin ,  Shih-Fang Hong ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq

    IPC: H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/3086 ,  H01L21/3081

    Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.

    Abstract translation: 本发明提供一种形成沟槽的方法。 首先，在基板上形成心轴层，其中心轴层包括停止层和牺牲层。 在心轴层的至少一个侧壁上形成间隔物，然后在衬底上形成用于覆盖间隔物和心轴层的材料层。 在执行去除处理以除去材料层之外的间隔物和牺牲层的间隔; 去除间隔物以在剩余材料层和心轴中形成至少一个第一沟槽。

    Method of forming trenches
    13.
    发明授权
    Method of forming trenches 有权
    形成沟槽的方法

    公开(公告)号：US09384978B1

    公开(公告)日：2016-07-05

    申请号：US14636200

    申请日：2015-03-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chao-Hung Lin ,  Shih-Fang Hong ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq

    IPC: H01L21/76 ,  H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/3086 ,  H01L21/3081

    Abstract: The present invention provides a method for forming trenches. First, a mandrel layer is formed on a substrate, wherein the mandrel layer comprises a stop layer and a sacrificial layer. A spacer is formed on at least a sidewall of the mandrel layer, following by forming a material layer on the substrate for covering the spacer and the mandrel layer. After performing a removing process to remove apart of the material layer, apart of the spacer and the sacrificial layer; the spacer is removed to form at least one first trench in the remaining material layer and the mandrel.

    Abstract translation: 本发明提供一种形成沟槽的方法。 首先，在基板上形成心轴层，其中心轴层包括停止层和牺牲层。 在心轴层的至少一个侧壁上形成间隔物，然后在衬底上形成用于覆盖间隔物和心轴层的材料层。 在执行去除处理以除去材料层之外的间隔物和牺牲层的间隔; 去除间隔物以在剩余材料层和心轴中形成至少一个第一沟槽。

    METHOD FOR GENERATING LAYOUT PATTERN
    14.
    发明申请
    METHOD FOR GENERATING LAYOUT PATTERN 有权
    生成布局图案的方法

    公开(公告)号：US20150347657A1

    公开(公告)日：2015-12-03

    申请号：US14822907

    申请日：2015-08-11

    Applicant: United Microelectronics Corp.

    Inventor： Po-Chao Tsao ,  Shih-Fang Hong ,  Chia-Wei Huang ,  Ming-Jui Chen ,  Shih-Fang Tzou ,  Ming-Te Wei

    IPC: G06F17/50 ,  G03F1/36

    CPC classification number: G06F17/5068 ,  G03F1/144 ,  G03F1/36

    Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.

    Abstract translation: 生成包括FinFET结构布局的布局图案的方法包括以下处理。 首先，将包括具有简单整数比例的间距的子图案的布局图案提供给计算机系统。 然后将子图案分类为第一子图案和第二子图案。 之后，产生第一条纹图案和至少一个第二条纹图案。 第一条形图案的纵向边缘与第一子图案的纵向边缘对准，并且第一条纹图案具有相等的间距和宽度。 第二条纹图案的位置对应于空白图案的位置，第二条纹图案的间距或宽度不同于第一条纹图案的间距或宽度。 最后，将第一条纹图案和第二条纹图案输出到光掩模。

    Method of forming Fin-FET
    15.
    发明申请
    Method of forming Fin-FET 有权
    Fin-FET的形成方法

    公开(公告)号：US20150064869A1

    公开(公告)日：2015-03-05

    申请号：US14018439

    申请日：2013-09-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

    IPC: H01L29/66

    CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/6681

    Abstract: The present invention provides a method of forming Fin-FET. A substrate with an active region and a dummy region are defined thereon. A plurality of first fins and second fins are formed in the active region, and a plurality of dummy fins are formed in the dummy region and the active region. A first active region is provided in the active region. A revised first active region is formed by extending the first active region to cover at least one adjacent dummy fin. Next, a first dummy region is provided in the dummy region. A first mask layout is formed by combining the revised first active region and the first dummy region. A first patterned mask layer is formed by using the first mask layout. A first epitaxial process is performed for the first fins and the dummy fins exposed by the first patterned mask layer.

    Abstract translation: 本发明提供一种形成Fin-FET的方法。 在其上限定具有有源区和虚拟区的衬底。 多个第一鳍片和第二鳍片形成在有源区域中，并且在虚拟区域和有源区域中形成多个虚设翅片。 在活动区域​​中设置第一有源区域。 经修改的第一有源区通过延伸第一有源区以覆盖至少一个相邻的虚拟鳍形成。 接下来，在虚拟区域中设置第一虚拟区域。 通过组合经修改的第一有源区和第一伪区形成第一掩模布局。 通过使用第一掩模布局形成第一图案化掩模层。 对由第一图案化掩模层暴露的第一鳍片和虚拟鳍片执行第一外延工艺。

    Semiconductor fin-shaped structure and manufacturing process thereof
    16.
    发明授权
    Semiconductor fin-shaped structure and manufacturing process thereof 有权
    半导体鳍状结构及其制造工艺

    公开(公告)号：US08802521B1

    公开(公告)日：2014-08-12

    申请号：US13909101

    申请日：2013-06-04

    Applicant: United Microelectronics Corp.

    Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Shih-Fang Hong

    IPC: H01L21/336 ,  H01L29/06 ,  H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/3086 ,  H01L29/6681 ,  H01L29/7851

    Abstract: The present invention provides a method for forming a fin structure comprising the following steps: first, a substrate is provided and a plurality of fin structures, a plurality of first dummy fin structures and a plurality of second dummy fin structures are formed on the substrate; a first patterned photoresist is used as a hard mask to perform a first etching process to remove each first dummy fin structure; then a second patterned photoresist is used as a hard mask to perform a second etching process to remove each second dummy fin structure, wherein the pattern density of the first patterned photoresist is higher than the pattern density of the second patterned.

    Abstract translation: 本发明提供一种形成翅片结构的方法，包括以下步骤：首先，提供基板，并在基板上形成多个翅片结构，多个第一虚拟翅片结构和多个第二虚拟翅片结构; 使用第一图案化的光致抗蚀剂作为硬掩模来执行第一蚀刻工艺以去除每个第一虚拟鳍结构; 然后使用第二图案化的光刻胶作为硬掩模来执行第二蚀刻工艺以去除每个第二虚拟鳍片结构，其中第一图案化光刻胶的图案密度高于第二图案化图案的图案密度。

    Semiconductor device
    20.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09373719B2

    公开(公告)日：2016-06-21

    申请号：US14027334

    申请日：2013-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Fang Hong ,  Chung-Yi Chiu

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/785 ,  H01L29/6681

    Abstract: A semiconductor device is provided. The semiconductor device includes an active fin region, at least a gate strip, and a dummy fin region. The active fin region comprises at least an active fin. The gate strip is formed on the active fin region and extending across the active fin. The dummy fin region, comprising a plurality of dummy fins, is formed on two sides of the active fin region, and the dummy fins are formed on two sides of the gate strip.

    Abstract translation: 提供半导体器件。 半导体器件包括有源鳍片区域，至少栅极条和伪鳍片区域。 活性鳍片区域至少包括活性鳍片。 栅极条形成在有源鳍片区域上并延伸穿过有源鳍片。 在活动鳍片区域的两侧形成有包括多个虚设翅片的虚拟鳍片区域，并且虚设翅片形成在栅极条的两侧。

Patent Agency Ranking