公开(公告)号：US20230282740A1

公开(公告)日：2023-09-07

申请号：US18195347

申请日：2023-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462

Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.

公开(公告)号：US11688790B2

公开(公告)日：2023-06-27

申请号：US17143135

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US11581438B2

公开(公告)日：2023-02-14

申请号：US16992061

申请日：2020-08-12

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

公开(公告)号：US20230017965A1

公开(公告)日：2023-01-19

申请号：US17956772

申请日：2022-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US20220189770A1

公开(公告)日：2022-06-16

申请号：US17147477

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Che Feng ,  Hsuan-Tai Hsu ,  Chun-Yu Chen ,  Wei-Hao Huang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/762

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.

公开(公告)号：US11189793B2

公开(公告)日：2021-11-30

申请号：US16589148

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Ting-An Chien

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.

公开(公告)号：US20210273089A1

公开(公告)日：2021-09-02

申请号：US17321517

申请日：2021-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Hsuan Chang ,  Chih-Wei Chang ,  Chi-Hsuan Cheng ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y

公开(公告)号：US12089512B2

公开(公告)日：2024-09-10

申请号：US18242550

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/00 ,  H10N70/028 ,  H10N70/041 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US11793091B2

公开(公告)日：2023-10-17

申请号：US17114438

申请日：2020-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L45/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/00 ,  H10N70/028 ,  H10N70/041 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US11723287B2

公开(公告)日：2023-08-08

申请号：US17956772

申请日：2022-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.