公开(公告)号：US20230163128A1

公开(公告)日：2023-05-25

申请号：US17556972

申请日：2021-12-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8258 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/7869 ,  H01L21/02565 ,  H01L21/8258 ,  H01L29/66969

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20220209009A1

公开(公告)日：2022-06-30

申请号：US17159166

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Nien-Chung Li ,  Chang-Po Hsiung

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

公开(公告)号：US11101381B2

公开(公告)日：2021-08-24

申请号：US16601364

申请日：2019-10-14

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

公开(公告)号：US20210167208A1

公开(公告)日：2021-06-03

申请号：US16711442

申请日：2019-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chang-Po Hsiung ,  Shin-Hung Li

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

公开(公告)号：US20250142841A1

公开(公告)日：2025-05-01

申请号：US18515299

申请日：2023-11-21

Applicant: United Microelectronics Corp.

Inventor： Shin-Hung Li

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/786

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first electrode, a second electrode, an insulating layer, a channel layer, a gate dielectric layer, a source electrode and a drain electrode. The first electrode is disposed on a substrate. The second electrode is disposed on the first electrode. The insulating layer is disposed between the first electrode and the second electrode. The channel layer is disposed on the second electrode. The gate dielectric layer is disposed between the channel layer and the second electrode. The source electrode is electrically connected to the first electrode and the channel layer. The drain electrode is electrically connected to the channel layer.

公开(公告)号：US20250081573A1

公开(公告)日：2025-03-06

申请号：US18369815

申请日：2023-09-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/66 ,  H01L29/78

Abstract: A middle voltage transistor structure includes a substrate. A gate structure is disposed on the substrate. A source lightly doped region and a drain lightly doped region are disposed within the substrate at two sides of the gate structure. A conductive structure contacts the lightly drain doped region. A first spacer surrounds the gate structure and a second spacer surrounds the conductive structure. The first spacer contacts the second spacer.

公开(公告)号：US20250079168A1

公开(公告)日：2025-03-06

申请号：US18378666

申请日：2023-10-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Shin-Hung Li ,  Shan-Shi Huang

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first oxide layer and a second oxide layer. The substrate has a first region and a second region. The first oxide layer is disposed on the first region. The first oxide layer includes a first thermal oxide layer and a first deposited oxide layer, and a portion of the first thermal oxide layer is formed by a pad oxide layer. The second oxide layer is disposed on the second region. The second oxide layer includes a second thermal oxide layer and a second deposited oxide layer.

公开(公告)号：US20240347338A1

公开(公告)日：2024-10-17

申请号：US18755651

申请日：2024-06-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L21/02 ,  H01L21/8258 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02565 ,  H01L21/8258 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides a semiconductor structure, including a substrate, a thin-film transistor (TFT) on the substrate, wherein the thin-film transistor including a TFT channel layer, a first source and a first drain in the TFT channel layer and a first capping layer on the TFT channel layer. A MOSFET is on the substrate, with a second gate, a second source and a second drain on two sides of the second gate and a second capping layer on the second gate, wherein top surfaces of the second capping layer and the first capping layer are leveled, and a first ILD layer is on the first capping layer and the second capping layer, wherein the first ILD layer and the first capping layer function collectively as a gate dielectric layer for the TFT.

公开(公告)号：US20230253496A1

公开(公告)日：2023-08-10

申请号：US17688821

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Hung Li

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/42392

Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor and a second transistor. The substrate includes a high-voltage region and a low-voltage region. The first transistor is disposed on the HV region, and includes a first gate dielectric layer disposed on a first base, and a first gate electrode on the first gate dielectric layer. The first gate dielectric layer includes a composite structure having a first dielectric layer and a second dielectric layer stacked sequentially. The second transistor is disposed on the LV region, and includes a fin shaped structure protruded from a second base on the substrate, and a second gate electrode disposed on the fin shaped structure. The first dielectric layer covers sidewalls of the second gate electrode and a top surface of the first dielectric layer is even with a top surface of the second gate electrode.

公开(公告)号：US20220223720A1

公开(公告)日：2022-07-14

申请号：US17160427

申请日：2021-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsung-Yu Yang ,  Shin-Hung Li ,  Ruei-Jhe Tsao ,  Ta-Wei Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.