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    Manufacturing method of interconnection structure
    11.
    发明授权
    Manufacturing method of interconnection structure 有权

    公开(公告)号：US10141224B2

    公开(公告)日：2018-11-27

    申请号：US15821666

    申请日：2017-11-22

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

    IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

    Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.

    MANUFACTURING METHOD OF INTERCONNECTION STRUCTURE
    12.
    发明申请
    MANUFACTURING METHOD OF INTERCONNECTION STRUCTURE 审中-公开

    公开(公告)号：US20180096889A1

    公开(公告)日：2018-04-05

    申请号：US15821666

    申请日：2017-11-22

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Yin-Po Hung ,  Ra-Min Tain ,  Yu-Hua Chen

    IPC: H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48

    CPC classification number: H01L21/76879 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827

    Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.

    Circuit board structure and method for manufacturing the same
    15.
    发明授权
    Circuit board structure and method for manufacturing the same 有权
    电路板结构及其制造方法

    公开(公告)号：US09578742B1

    公开(公告)日：2017-02-21

    申请号：US14821819

    申请日：2015-08-10

    Applicant: Unimicron Technology Corp.

    Inventor： Shih-Liang Cheng ,  Dyi-Chung Hu ,  Yu-Hua Chen

    IPC: H05K1/11 ,  H05K3/00 ,  H05K1/02 ,  H05K3/40 ,  H05K1/09 ,  H05K1/18

    CPC classification number: H05K1/11 ,  H05K1/0298 ,  H05K1/182 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/007 ,  H05K3/0097 ,  H05K3/045 ,  H05K3/107 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0195 ,  H05K2203/025 ,  H05K2203/107 ,  H05K2203/1476

    Abstract: A method for manufacturing a circuit board structure is provided. First, a first circuit layer is formed on a carrier. Then, a first dielectric layer is formed on the carrier and the first circuit layer. Thereafter, at least one first hole is formed in the first dielectric layer to expose a portion of the first circuit layer. Then, a second dielectric layer is formed on the first dielectric layer and the first circuit layer. Thereafter, at least one trench and at least one second hole are formed in the second dielectric layer, in which the trench exposes a portion of the first dielectric layer, and the second hole exposes the portion of the first circuit layer. The second hole is disposed in the first hole. Then, a metal layer is formed to fill the trench and the second hole.

    Abstract translation: 提供一种制造电路板结构的方法。 首先，在载体上形成第一电路层。 然后，在载体和第一电路层上形成第一电介质层。 此后，在第一电介质层中形成至少一个第一孔以暴露第一电路层的一部分。 然后，在第一电介质层和第一电路层上形成第二电介质层。 此后，在第二电介质层中形成至少一个沟槽和至少一个第二孔，其中沟槽露出第一电介质层的一部分，并且第二孔露出第一电路层的部分。 第二孔设置在第一孔中。 然后，形成金属层以填充沟槽和第二孔。

    METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE
    16.
    发明申请
    METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE 有权
    制造插销器，插件和芯片包装结构的方法

    公开(公告)号：US20160190050A1

    公开(公告)日：2016-06-30

    申请号：US14583755

    申请日：2014-12-28

    Applicant: Unimicron Technology Corp.

    Inventor： Ra-Min Tain ,  Dyi-Chung Hu ,  Yu-Hua Chen

    IPC: H01L23/498 ,  H01L21/3105 ,  H01L21/48

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.

    Abstract translation: 一种用于制造插入件的方法包括以下步骤。 导电珠填充在基板的盲孔中，并且每个导电珠的焊料层熔化，以在盲孔中形成焊料柱。 每个导电珠的金属球镶嵌在相应的焊料柱中，使得焊接柱和镶嵌在其中的金属球构成导电的通孔。 基板的两个表面被平坦化，使得导电通孔的两个端部分别暴露于基板的两个表面，并分别与基板的两个表面齐平。 在衬底的每个表面处制造再分布层，使得每个导电通孔的两端分别连接重新分布层。 此外，还提供了应用了插入器的插入器和芯片封装结构。

    INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF
    17.
    发明申请
    INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    嵌入式基板及其制造方法

    公开(公告)号：US20140138142A1

    公开(公告)日：2014-05-22

    申请号：US14164245

    申请日：2014-01-26

    Applicant: UNIMICRON TECHNOLOGY CORP.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H05K3/10 ,  H05K1/11

    CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

    Method for manufacturing an interposer, interposer and chip package structure
    19.
    发明授权
    Method for manufacturing an interposer, interposer and chip package structure 有权
    用于制造插入件，插入件和芯片封装结构的方法

    公开(公告)号：US09368442B1

    公开(公告)日：2016-06-14

    申请号：US14583755

    申请日：2014-12-28

    Applicant: Unimicron Technology Corp.

    Inventor： Ra-Min Tain ,  Dyi-Chung Hu ,  Yu-Hua Chen

    IPC: H01L23/498 ,  H01L21/48 ,  H01L21/3105

    CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49833 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.

    Abstract translation: 一种用于制造插入件的方法包括以下步骤。 导电珠填充在基板的盲孔中，并且每个导电珠的焊料层熔化，以在盲孔中形成焊料柱。 每个导电珠的金属球镶嵌在相应的焊料柱中，使得焊接柱和镶嵌在其中的金属球构成导电的通孔。 基板的两个表面被平坦化，使得导电通孔的两个端部分别暴露于基板的两个表面，并分别与基板的两个表面齐平。 在衬底的每个表面处制造再分布层，使得每个导电通孔的两端分别连接重新分布层。 此外，还提供了应用了插入器的插入器和芯片封装结构。

    Interposed substrate and manufacturing method thereof
    20.
    发明授权
    Interposed substrate and manufacturing method thereof 有权
    基片及其制造方法

    公开(公告)号：US09282646B2

    公开(公告)日：2016-03-08

    申请号：US14164245

    申请日：2014-01-26

    Applicant: Unimicron Technology Corp.

    Inventor： Dyi-Chung Hu ,  Ming-Chih Chen ,  Tzyy-Jang Tseng

    IPC: H05K1/11 ,  H05K3/10 ,  C25D1/00 ,  H05K3/46 ,  H05K3/42

    CPC classification number: H01L21/4857 ,  C25D1/003 ,  C25D5/022 ,  C25D5/34 ,  C25D5/48 ,  C25D7/12 ,  H05K1/113 ,  H05K3/10 ,  H05K3/424 ,  H05K3/4647 ,  H05K3/4682 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/49155

    Abstract: A manufacturing method of an interposed substrate is provided. A metal-stacked layer comprising a first metal layer, an etching stop layer and a second metal layer is formed. A patterned conductor layer is formed on the first metal layer, wherein the patterned conductor layer exposes a portion of the first metal layer. A plurality of conductive pillars is formed on the patterned conductor layer, wherein the conductive pillars are separated from each other and stacked on a portion of the patterned conductor layer. An insulating material layer is formed on the metal-stacked layer, wherein the insulating material layer covers the portion of the first metal layer and encapsulates the conductive pillars and the other portion of the patterned conductor layer. The metal-stacked layer is removed to expose a lower surface opposite to an upper surface of the insulating material layer and a bottom surface of the patterned conductor layer.

    Abstract translation: 提供了一种插入式基板的制造方法。 形成包括第一金属层，蚀刻停止层和第二金属层的金属层叠层。 图案化的导体层形成在第一金属层上，其中图案化的导体层露出第一金属层的一部分。 在图案化的导体层上形成多个导电柱，其中导电柱彼此分离并堆叠在图案化的导体层的一部分上。 在金属堆叠层上形成绝缘材料层，其中绝缘材料层覆盖第一金属层的部分并且封装导电柱和图案化导体层的另一部分。 去除金属层叠层以露出与绝缘材料层的上表面相反的下表面和图案化导体层的底表面。

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