公开(公告)号：US11812667B2

公开(公告)日：2023-11-07

申请号：US17341316

申请日：2021-06-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.

公开(公告)号：US20230262993A1

公开(公告)日：2023-08-17

申请号：US18304335

申请日：2023-04-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US11690230B2

公开(公告)日：2023-06-27

申请号：US17345806

申请日：2021-06-11

Applicant: United Microelectronics Corp.

Inventor： Cheng-Yi Lin ,  Tang Chun Weng ,  Chia-Chang Hsu ,  Yung Shen Chen ,  Chia-Hung Lin

IPC: H10B61/00 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H01L23/5283 ,  H10N50/01 ,  H10N50/80

Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.

公开(公告)号：US20220392768A1

公开(公告)日：2022-12-08

申请号：US17341183

申请日：2021-06-07

Applicant: United Microelectronics Corp.

Inventor： Yi Jing Wang ,  Chia-Chang Hsu ,  Chien-Hao Chen ,  Chang-Mao Wang ,  Chun-Chi Yu

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

公开(公告)号：US20220352459A1

公开(公告)日：2022-11-03

申请号：US17867702

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16

Abstract: A semiconductor device includes a substrate comprising a MTJ region and a logic region, a magnetic tunneling junction (MTJ) on the MTJ region, and a contact plug on the logic region. Preferably, the MTJ includes a bottom electrode layer having a gradient concentration, a free layer on the bottom electrode layer, and a top electrode layer on the free layer.

公开(公告)号：US11430946B2

公开(公告)日：2022-08-30

申请号：US17064607

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16 ,  H01L43/10

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

公开(公告)号：US20220216397A1

公开(公告)日：2022-07-07

申请号：US17705404

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

IPC: H01L43/12 ,  H01L23/544 ,  H01L43/02 ,  H01L27/22

Abstract: A method for forming a semiconductor structure includes the steps of providing a substrate having a device region and an alignment mark region, forming a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer, forming a conductive via in the second dielectric layer on the device region, forming a mask layer on the second dielectric layer, etching the second dielectric layer and the first dielectric layer through an opening of the mask layer on the alignment mark region to form a first trench through the second dielectric layer and an upper portion of the first dielectric layer and a plurality of second trenches in the first dielectric layer directly under the first trench. Afterward, a memory stack structure is formed on the second dielectric layer, covering the conductive via and filling into the first trench and the second trenches.

公开(公告)号：US11335729B2

公开(公告)日：2022-05-17

申请号：US17074643

申请日：2020-10-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Hung-Chan Lin ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G11C11/16 ,  H01L27/22 ,  H01L23/48 ,  H01L43/12 ,  H01L23/544 ,  H01L21/321 ,  H01L21/762 ,  H01L23/485

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

公开(公告)号：US20210167282A1

公开(公告)日：2021-06-03

申请号：US17152703

申请日：2021-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Rai-Min Huang

IPC: H01L43/12 ,  H01L23/544 ,  H01L27/22 ,  H01L43/02

Abstract: A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.