公开(公告)号：US20220037344A1

公开(公告)日：2022-02-03

申请号：US17005285

申请日：2020-08-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Hung-Hsun Shuai

IPC: H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11565

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

公开(公告)号：US09773800B1

公开(公告)日：2017-09-26

申请号：US15250930

申请日：2016-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L21/336 ,  H01L29/792 ,  H01L31/119 ,  H01L27/11568 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L21/32133 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: The present invention provides a non-volatile memory structure, which includes a substrate, a gate dielectric layer disposed on the substrate, two charge trapping layers, disposed on two sides of the gate dielectric layer respectively and disposed on the substrate, a gate conductive layer disposed on the gate dielectric layer and on the charge trapping layers, wherein a sidewall of the gate conductive layer is aligned with a sidewall of one of the two charge trapping layers, and at least one vertical oxide layer, disposed beside the sidewall of the gate conductive layer.

公开(公告)号：US20240072129A1

公开(公告)日：2024-02-29

申请号：US18504165

申请日：2023-11-08

Applicant: United Microelectronics Corp.

Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/49 ,  H01L29/66 ,  H01L29/788

CPC classification number: H01L29/40114 ,  H01L21/76224 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/788 ,  H01L21/31051

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

公开(公告)号：US11737265B2

公开(公告)日：2023-08-22

申请号：US17888511

申请日：2022-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Hung-Hsun Shuai

IPC: H01L21/00 ,  H10B41/30 ,  H10B41/10 ,  H10B43/10 ,  H10B43/30

CPC classification number: H10B41/30 ,  H10B41/10 ,  H10B43/10 ,  H10B43/30

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

公开(公告)号：US20220278238A1

公开(公告)日：2022-09-01

申请号：US17747976

申请日：2022-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H01L29/788 ,  H01L21/28 ,  H01L29/08 ,  H01L21/265 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

公开(公告)号：US10373861B1

公开(公告)日：2019-08-06

申请号：US16026077

申请日：2018-07-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Ying Hsieh ,  Chih-Jung Chen ,  Chien-Hung Chen ,  Chih-Yueh Li ,  Cheng-Pu Chiu ,  Shih-Min Lu ,  Yung-Sung Lin

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor structure includes a substrate having a plurality of fin structures thereon, an isolation oxide structure in the substrate between adjacent two of the plurality of fin structures, a gate disposed on the plurality of fin structures, a gate dielectric layer disposed between the plurality of fin structures and the gate, and a source/drain doped region in each of the plurality of fin structures. The isolation oxide structure has a concave, curved top surface.

公开(公告)号：US20170018649A1

公开(公告)日：2017-01-19

申请号：US15279410

申请日：2016-09-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Jung Chen ,  Tzu-Ping Chen

IPC: H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  G11C16/14 ,  G11C16/04

CPC classification number: H01L29/7887 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a dielectric stack is formed on the substrate, in which the dielectric stack includes a first silicon oxide layer and a first silicon nitride layer. Next, the dielectric stack is patterned, part of the first silicon nitride layer is removed to form two recesses under two ends of the first silicon nitride layer, second silicon oxide layers are formed in the two recesses, a spacer is formed on the second silicon oxide layers, and third silicon oxide layers are formed adjacent to the second silicon oxide layers.

Abstract translation: 公开了半导体器件的制造方法。 首先，提供基板，并且在基板上形成电介质堆叠，其中电介质叠层包括第一氧化硅层和第一氮化硅层。 接下来，对电介质堆叠进行构图，去除第一氮化硅层的一部分以在第一氮化硅层的两端形成两个凹部，在两个凹部中形成第二氧化硅层，在第二硅上形成间隔物 氧化物层和与第二氧化硅层相邻的第三氧化硅层。

公开(公告)号：US20240334693A1

公开(公告)日：2024-10-03

申请号：US18739352

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Jen Yeh ,  Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H10B41/35 ,  H01L29/423 ,  H01L29/66 ,  H10B41/60

CPC classification number: H10B41/35 ,  H01L29/42328 ,  H01L29/66825 ,  H10B41/60

Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

公开(公告)号：US11855156B2

公开(公告)日：2023-12-26

申请号：US17855700

申请日：2022-06-30

Applicant: United Microelectronics Corp.

Inventor： Chih-Jung Chen ,  Yu-Jen Yeh

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/788 ,  H01L21/3105

CPC classification number: H01L29/40114 ,  H01L21/76224 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/788 ,  H01L21/31051

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

公开(公告)号：US11705526B2

公开(公告)日：2023-07-18

申请号：US17747976

申请日：2022-05-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Hsun Shuai ,  Chih-Jung Chen

IPC: H01L29/788 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L21/28 ,  H01L29/423 ,  H10B41/30 ,  H10B41/10 ,  H01L29/66

CPC classification number: H01L29/7881 ,  H01L21/26513 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.