公开(公告)号：US09666507B2

公开(公告)日：2017-05-30

申请号：US14556215

申请日：2014-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chien-Li Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating through-substrate structure is disclosed. The method includes the steps of: providing a substrate; forming a through-substrate hole and a through-substrate trench in the substrate; and forming a metal layer in the through-substrate hole and the through-substrate trench for forming a through-substrate via and a through-substrate conductor having a void therein.

公开(公告)号：US09343359B2

公开(公告)日：2016-05-17

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L23/525

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US12034038B2

公开(公告)日：2024-07-09

申请号：US18119043

申请日：2023-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chu-Fu Lin ,  Chun-Hung Chen

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/91

Abstract: A method for manufacturing a capacitor structure is provided. A substrate having a first side and a second side opposite to the first side is provided. A plurality of first trenches are formed on the first side. A first capacitor is formed extending along the first side and into the first trenches. A plurality of second trenches are formed on the second side. A second capacitor is formed extending along the second side and into the second trenches.

公开(公告)号：US11699646B2

公开(公告)日：2023-07-11

申请号：US17943215

申请日：2022-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L27/08 ,  H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/48 ,  H01L27/01 ,  H01L21/768

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L27/01 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/16113 ,  H01L2224/16147

Abstract: A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

公开(公告)号：US11482485B2

公开(公告)日：2022-10-25

申请号：US17073392

申请日：2020-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin

IPC: H01L27/08 ,  H01L23/498 ,  H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L21/48 ,  H01L27/01 ,  H01L21/768

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an interposer substrate having an upper surface and a lower surface that is opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least a through-silicon via is formed in the interposer substrate. An end of the guard ring and an end of the through-silicon via that are near the upper surface of the interposer substrate are flush with each other.

公开(公告)号：US20190221528A1

公开(公告)日：2019-07-18

申请号：US16361880

申请日：2019-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Chu-Fu Lin ,  Ming-Tse Lin

IPC: H01L23/64 ,  H01L23/31

Abstract: A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.

公开(公告)号：US10323332B2

公开(公告)日：2019-06-18

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D7/12 ,  C25D5/00 ,  C25D3/38 ,  C25D5/10 ,  C25D5/54 ,  H01L21/288 ,  H01L21/768

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

公开(公告)号：US20190013259A1

公开(公告)日：2019-01-10

申请号：US15642349

申请日：2017-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Teng-Chuan Hu ,  Chun-Hung Chen ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Ming-Tse Lin

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.

公开(公告)号：US20160319450A1

公开(公告)日：2016-11-03

申请号：US15206321

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ling Lin ,  Yen-Liang Lu ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Hung Chen ,  Tsun-Min Cheng ,  Chi-Ray Tsai

IPC: C25D5/54 ,  H01L21/768 ,  C25D7/12 ,  H01L21/288 ,  C25D3/38 ,  C25D5/10

CPC classification number: C25D5/54 ,  C25D3/38 ,  C25D5/00 ,  C25D5/10 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76879

Abstract: An electrical chemical plating process is provided. A semiconductor structure is provided in an electrical plating platform. A pre-electrical-plating step is performed wherein the pre-electrical-plating step is carried out under a fixed voltage environment and lasts for 0.2 to 0.5 seconds after the current is above the threshold current of the electrical plating platform. After the pre-electrical-plating step, a first electrical plating step is performed on the semiconductor structure.

Abstract translation: 提供电化学镀工艺。 半导体结构设置在电镀平台中。 进行预电镀步骤，其中预电镀步骤在固定电压环境下进行，并且在电流高于电镀平台的阈值电流之后持续0.2至0.5秒。 在预电镀步骤之后，对半导体结构进行第一电镀步骤。

公开(公告)号：US20150179580A1

公开(公告)日：2015-06-25

申请号：US14139879

申请日：2013-12-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Yung-Chang Lin ,  Ming-Tse Lin

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating hybrid interconnect structure is disclosed. The method includes the steps of: providing a material layer; forming a through-silicon hole in the material layer; forming a patterned resist on the material layer, wherein the patterned resist comprises at least an opening for exposing the through-silicon hole; and forming a conductive layer to fill the through-silicon hole and the opening in the patterned resist.

Abstract translation: 公开了一种用于制造混合互连结构的方法。 该方法包括以下步骤：提供材料层; 在所述材料层中形成通孔; 在所述材料层上形成图案化的抗蚀剂，其中所述图案化的抗蚀剂至少包括用于暴露所述通孔的孔; 以及形成导电层以填充图案化的抗蚀剂中的通孔和孔。