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    Fabrication method of semiconductor structure
    11.
    发明授权
    Fabrication method of semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US09397190B2

    公开(公告)日：2016-07-19

    申请号：US14341838

    申请日：2014-07-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

    IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

    CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

    Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

    Method of forming semiconductor device
    12.
    发明授权
    Method of forming semiconductor device 有权

    公开(公告)号：US10529856B2

    公开(公告)日：2020-01-07

    申请号：US16028187

    申请日：2018-07-05

    Applicant: United Microelectronics Corp.

    Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/308

    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

    FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF
    15.
    发明申请
    FIN-SHAPED STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
    精细形状结构及其制造方法

    公开(公告)号：US20160071844A1

    公开(公告)日：2016-03-10

    申请号：US14512475

    申请日：2014-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

    IPC: H01L27/088 ,  H01L21/308 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8236

    CPC classification number: H01L21/308 ,  H01L21/02238 ,  H01L21/30604 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66818

    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

    Abstract translation: 鳍状结构包括具有位于第一区域中的第一鳍状结构的基板和位于第二区域中的第二鳍状结构，其中第二鳍状结构包括梯形横截面轮廓部分 。 本发明还提供了形成该鳍状结构的两种方法。 在一种情况下，提供具有第一鳍状结构和第二鳍状结构的基板。 执行处理工艺以改变第二鳍状结构的顶部的外表面，从而形成修改部分。 进行去除处理以通过对第一鳍状结构和第二鳍状结构以及改性部分的高去除选择性去除改性部分，由此第二鳍状结构具有梯形横截面 形成轮廓部分。

    MOS TRANSISTOR AND SEMICONDUCTOR PROCESS FOR FORMING EPITAXIAL STRUCTURE
    16.
    发明申请
    MOS TRANSISTOR AND SEMICONDUCTOR PROCESS FOR FORMING EPITAXIAL STRUCTURE 审中-公开
    用于形成外延结构的MOS晶体管和半导体工艺

    公开(公告)号：US20160049496A1

    公开(公告)日：2016-02-18

    申请号：US14495907

    申请日：2014-09-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

    CPC classification number: H01L29/66553 ,  H01L21/02057 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

    Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.

    Abstract translation: 提供了包括栅极结构，外延隔离物和外延结构的MOS晶体管。 栅极结构设置在基板上。 除了栅极结构之外，外延衬垫设置在衬底上，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 外延结构除了外延间隔物之外还设置在基板中。 半导体工艺包括用于形成外延结构的以下步骤。 在基板上形成栅极结构。 除了用于限定外延结构的位置的栅极结构之外，在衬底上形成外延衬垫，其中外延衬垫包括硅和氮，并且氮与硅之比大于1.3。 该外延结构除了外延间隔物外还形成在基板中。

    Semiconductor Structure
    19.
    发明申请
    Semiconductor Structure 有权
    半导体结构

    公开(公告)号：US20160163797A1

    公开(公告)日：2016-06-09

    申请号：US14594159

    申请日：2015-01-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Chia-Jong Liu ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Man-Ling Lu ,  Yi-Wei Chen ,  Jhen-Cyuan Li

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

    Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.

    Abstract translation: 本发明提供一种半导体结构，其包括衬底，栅极结构，源极/漏极区域和至少位错。 栅极结构设置在基板上。 源极/漏极区域在栅极结构的两侧设置在衬底中。 位错位于源极/漏极区域中，并且与源极/漏极区域的中间轴线不对称。

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