公开(公告)号：US11133465B2

公开(公告)日：2021-09-28

申请号：US16727853

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L45/00 ,  G11C13/00

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Lower memory cells are formed above and in contact with the lower bit line. Each lower memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. Parallel word lines in a same plane are formed above and in contact with the lower memory cells. Each word line is perpendicular to the lower bit line. Upper memory cells are formed above and in contact with the word lines. Each upper memory cell includes stacked a PCM element, a selector, and electrodes. An upper bit line is formed above and in contact with the upper memory cells. The upper bit line is perpendicular to each word line. An upper bit line contact is formed above and in contact with the upper bit line. At least one of the lower bit line contact and the upper bit line contact is disposed inclusively between the lower and upper memory cells in a plan view.

公开(公告)号：US20210233916A1

公开(公告)日：2021-07-29

申请号：US17228496

申请日：2021-04-12

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  H01L27/108

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US11063215B2

公开(公告)日：2021-07-13

申请号：US16727852

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A three-dimensional (3D) memory device includes parallel lower and upper bit lines, parallel word lines, lower and upper memory cells, a lower bit line contact in contact with the lower bit line, and an upper bit line contact in contact with the upper bit line. The parallel word lines are in a same plane between the lower and the upper bit lines. Each word line is perpendicular to the lower and upper bit lines. Each lower memory cell is disposed at an intersection of the lower bit line and a respective word line. Each upper memory cell is disposed at an intersection of the upper bit line and a respective word line. Each lower or upper memory cell includes stacked a phase-change memory (PCM) element, a selector, and electrodes. At least one of the lower and upper bit line contacts is disposed inclusively between the lower and upper memory cells in a plan view.

公开(公告)号：US20210151414A1

公开(公告)日：2021-05-20

申请号：US17157776

申请日：2021-01-25

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of DRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer in are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US20210134748A1

公开(公告)日：2021-05-06

申请号：US16727885

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.

公开(公告)号：US20210111122A1

公开(公告)日：2021-04-15

申请号：US16727869

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/538 ,  H01L23/498 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an interposer structure vertically between the first and second semiconductor structures. The first semiconductor structure includes a plurality of logic process-compatible devices and a first bonding layer comprising a plurality of first bonding contacts. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer comprising a plurality of second bonding contacts. The interposer structure includes a first interposer bonding layer having a plurality of first interposer contacts disposed at a first side of the interposer structure, and a second interposer bonding layer having a plurality of second interposer contacts disposed at a second side opposite of the first side of the interposer structure. The first interposer contacts is conductively connected to the second interposer contacts.

公开(公告)号：US20200350287A1

公开(公告)日：2020-11-05

申请号：US16669454

申请日：2019-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L25/065 ,  G11C13/00 ,  G11C16/04 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  G11C16/10

Abstract: Embodiments of three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of 3D PCM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20200328190A1

公开(公告)日：2020-10-15

申请号：US16727890

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20200328188A1

公开(公告)日：2020-10-15

申请号：US16669435

申请日：2019-10-30

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L21/78 ,  H01L25/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a processor, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20200258857A1

公开(公告)日：2020-08-13

申请号：US16292273

申请日：2019-03-04

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zongliang Huo ,  Jun Liu ,  Jifeng Zhu ,  Jun Chen ,  Zi Qun Hua ,  Li Hong Xiao

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/532 ,  H01L23/538 ,  H01L27/11582 ,  H01L27/1157 ,  H01L21/768

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact or the second bonding contact is made of an indiffusible conductive material.