公开(公告)号：US20130126950A1

公开(公告)日：2013-05-23

申请号：US13304235

申请日：2011-11-23

Applicant: Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Jun-Nan Nian ,  Li-Yen Fang ,  Yu-Ting Lin ,  Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L23/53209 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.

公开(公告)号：US20130010247A1

公开(公告)日：2013-01-10

申请号：US13300674

申请日：2011-11-21

Applicant: Chuan-Sheng Wei ,  Ming-Tao Chiang ,  Yu-Ting Lin ,  Maw-Song Chen ,  Wei-Ming Huang

Inventor： Chuan-Sheng Wei ,  Ming-Tao Chiang ,  Yu-Ting Lin ,  Maw-Song Chen ,  Wei-Ming Huang

IPC: G02F1/1343 ,  H05B33/14 ,  G02B26/00 ,  H05K1/18

CPC classification number: H01L29/41733 ,  G02F1/13624 ,  H01L27/124

Abstract: A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.

Abstract translation: 提供了包括像素电极和有源器件的像素阵列。 有源器件包括栅极，沟道层，源极，漏极，连接电极，第一分支部分和第二分支部分。 栅极与扫描线电连接。 位于栅极侧的沟道层与栅极电绝缘。 源极，漏极和连接电极设置在沟道层的一部分区域上。 设置在沟道层的一部分区域上的第一分支部分与连接电极的一端连接。 第一分支部分围绕位于通道层上的源。 设置在沟道层的一部分区域上的第二分支部分与连接电极的另一端连接。 第二分支部分围绕位于通道层上的漏极。

公开(公告)号：US08344471B2

公开(公告)日：2013-01-01

申请号：US12511789

申请日：2009-07-29

Applicant: Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

Inventor： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC: H01L31/00

CPC classification number: H01L27/14636 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/1464 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract translation: 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成相当大的通孔，称为大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US20120114198A1

公开(公告)日：2012-05-10

申请号：US12966581

申请日：2010-12-13

Applicant: Ting-Ting YANG ,  Yu-Ting Lin ,  Chun-Yen Cheng ,  Shih-Chun Chou

Inventor： Ting-Ting YANG ,  Yu-Ting Lin ,  Chun-Yen Cheng ,  Shih-Chun Chou

IPC: G06K9/00

CPC classification number: G06K9/00234 ,  G06K9/00288

Abstract: A facial image gender identification system is provided. The system includes a face database, an image capturing unit, a gender identification data generating unit, and a gender identification unit. The face database is for storing gender characteristic values and gender data corresponding to each of a plurality of training facial images respectively. The image capturing unit is for capturing at least one facial image. The gender identification data generating unit, coupled to the image capturing unit and the face database, is for receiving the facial image from the image capturing unit and calculating global feature values and local feature values of the facial image. The gender identification unit, coupled to the gender identification data generating unit and the face database, is for determining a gender identification result according the global feature values and local feature values, and the gender characteristic values and gender data stored in the face database.

Abstract translation: 提供面部图像性别识别系统。 该系统包括面部数据库，图像捕获单元，性别识别数据生成单元和性别识别单元。 面部数据库用于分别存储对应于多个训练面部图像中的每一个的性别特征值和性别数据。 图像捕获单元用于捕获至少一个面部图像。 耦合到图像拍摄单元和面部数据库的性别识别数据生成单元用于从图像捕获单元接收面部图像，并计算面部图像的全局特征值和局部特征值。 性别识别单元，耦合到性别识别数据生成单元和面部数据库，用于根据全局特征值和局部特征值以及存储在面部数据库中的性别特征值和性别数据来确定性别识别结果。

公开(公告)号：US20110155230A1

公开(公告)日：2011-06-30

申请号：US12965591

申请日：2010-12-10

Applicant: Hung-Chun Tsai ,  Chi-Lai Lee ,  Yu-Ting Lin ,  Yaw-Ming Tsai

Inventor： Hung-Chun Tsai ,  Chi-Lai Lee ,  Yu-Ting Lin ,  Yaw-Ming Tsai

IPC: H01L31/06 ,  H01L31/18

CPC classification number: H01L25/047 ,  H01L31/043 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

Abstract: A multi-bandgap solar cell is produced by using a transparent intercellular layer to bind two solar cells with different bandgaps. The intercellular layer has at least an adhesive layer.

Abstract translation: 通过使用透明细胞间层来结合具有不同带隙的两个太阳能电池来制造多带隙太阳能电池。 细胞间层至少具有粘合剂层。

公开(公告)号：US20100072635A1

公开(公告)日：2010-03-25

申请号：US12236190

申请日：2008-09-23

Applicant: Yian-Liang Kuo ,  Chien-Yi Chen ,  Yu-Ting Lin ,  Yung-Sheng Huang

Inventor： Yian-Liang Kuo ,  Chien-Yi Chen ,  Yu-Ting Lin ,  Yung-Sheng Huang

IPC: H01L23/544 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.

Abstract translation: 一种形成集成电路结构的方法包括提供具有第一半导体芯片，第二半导体芯片和在第一半导体芯片和第二半导体芯片之间并与之邻接的划线的晶片; 在划线中形成缺口，其中所述凹口具有不高于所述晶片中的半导体衬底的顶表面的底部; 在所述晶片上形成第一绝缘膜，其中所述第一绝缘膜延伸到所述凹口中; 从所述凹口的中心移除所述第一绝缘膜的一部分，其中所述第一绝缘膜的剩余部分包括所述凹口中的边缘; 并锯切晶片以分离第一半导体芯片和第二半导体芯片。

公开(公告)号：US20090121222A1

公开(公告)日：2009-05-14

申请号：US12354338

申请日：2009-01-15

Applicant: Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

Inventor： Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

IPC: H01L23/488

CPC classification number: H01L24/05 ,  H01L22/34 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

Abstract translation: 用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。 测试结构在制造时被集成到半导体器件中。 金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。 大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。 待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。 导电线电耦合到相同或交替地不同金属层的测试部分。 测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

公开(公告)号：US07180173B2

公开(公告)日：2007-02-20

申请号：US10718192

申请日：2003-11-20

Applicant: Yian-Liang Kuo ,  Yung-Sheng Huang ,  Yu-Ting Lin

Inventor： Yian-Liang Kuo ,  Yung-Sheng Huang ,  Yu-Ting Lin

IPC: H01L23/34 ,  H01L23/10

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/42 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming a heat spreader ball grid array package, and the resultant heat spreader ball grid array package, comprising the following steps. A semiconductor chip affixed to a ball grid substrate is provided. The semiconductor chip over the ball grid substrate is encased with a molding compound. A heat spreader is mounted over the ball grid substrate and spaced apart from the molding compound to form a gap. Thermal grease is placed into the gap, at least between the heat spreader and the molding compound, to form the heat spreader ball grid array package. It is also possible to place thermal grease over the molding compound and then mounting the heat spreader over the ball grid substrate.

Abstract translation: 一种形成散热器球栅阵列封装的方法，以及所得的散热器球栅阵列封装，包括以下步骤。 提供固定在球栅基板上的半导体芯片。 球形栅极衬底上的半导体芯片被模制化合物封装。 散热器安装在球栅基板上并与模塑料间隔开以形成间隙。 至少在散热器和模塑料之间，将热油脂放置在间隙中，形成散热器球栅阵列封装。 还可以将热油脂放置在模制化合物上，然后将散热器安装在球栅基板上。

公开(公告)号：US07125445B2

公开(公告)日：2006-10-24

申请号：US11085773

申请日：2005-03-21

Applicant: Kai-Pin Chou ,  Yun-I Liu ,  Yu-Ting Lin

Inventor： Kai-Pin Chou ,  Yun-I Liu ,  Yu-Ting Lin

IPC: C09D11/02 ,  C09B67/00 ,  B41J2/01

CPC classification number: C09D11/32 ,  C09B43/16

Abstract: A magenta inkjet ink composition with good pH value stability including at least one reactive red colorant; at least one azo red dye (such as M377); and an aqueous solution medium.

Abstract translation: 具有良好pH值稳定性的品红色喷墨油墨组合物，包括至少一种反应性红色着色剂; 至少一种偶氮红染料（如M377）; 和水溶液介质。

公开(公告)号：US06943103B2

公开(公告)日：2005-09-13

申请号：US10768848

申请日：2004-01-29

Applicant: Yia-Liang Kuo ,  Yu-Chang Lin ,  Yu-Ting Lin

Inventor： Yia-Liang Kuo ,  Yu-Chang Lin ,  Yu-Ting Lin

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: Novel methods for reducing shear stress applied to solder bumps on a flip chip. The methods are particularly applicable to reducing temperature-induced shear stress on solder bumps located adjacent to an empty space on a flip chip during high-temperature testing of the chip. According to a first embodiment, the method includes providing an anchoring solder bump in each empty space on the flip chip. The anchoring solder bumps impart additional structural integrity to the flip chip and prevent shear-induced detachment of solder bumps from the flip chip, particularly those solder bumps located adjacent to each anchoring solder bump. According to a second embodiment, the method includes providing an anchoring solder bump in the empty space and then connecting the anchoring solder bump to an adjacent solder bump on the chip using a solder bridge.

Abstract translation: 用于减少施加到倒装芯片上的焊料凸块的剪切应力的新方法。 该方法特别适用于在芯片的高温测试期间减少与倒装芯片上的空白空间相邻的焊料凸块上的温度诱导剪切应力。 根据第一实施例，该方法包括在倒装芯片上的每个空白空间中提供锚定焊​​料凸块。 锚定焊料凸块对倒装芯片赋予额外的结构完整性，并防止焊料凸块从倒装芯片，特别是位于每个锚定焊料凸块附近的焊料凸块的剪切引起的分离。 根据第二实施例，该方法包括在空间中提供锚定焊​​料凸块，然后使用焊接桥将锚定焊料凸块连接到芯片上的相邻焊料凸块。