公开(公告)号：US07928719B2

公开(公告)日：2011-04-19

申请号：US11970435

申请日：2008-01-07

Applicant: Haibo Zhang ,  Ligang Jia

Inventor： Haibo Zhang ,  Ligang Jia

IPC: G01R19/00

CPC classification number: G01R19/175 ,  H02M2001/0009

Abstract: A zero current detector for a DC-DC converter includes a first transistor having a drain, a gate, and a source for sensing the voltage of a first terminal of a power transistor; a second transistor having a drain, a gate, and a source for sensing the voltage of a second terminal of a power transistor; and a third transistor having a coupled gate and drain for receiving a reference current that is coupled to the gates of the first and second transistors and a source coupled to the source of the first transistor, wherein an output signal is provided by the drains of the first and second transistors. A load is coupled to the drains of the first and second transistors. The zero current detector also includes a fourth transistor having a current path coupled between the source of the second transistor and the second terminal of the power transistor and a gate for receiving a control signal.

Abstract translation: 用于DC-DC转换器的零电流检测器包括具有漏极，栅极和源极的第一晶体管，用于感测功率晶体管的第一端子的电压; 具有用于感测功率晶体管的第二端子的电压的漏极，栅极和源极的第二晶体管; 以及第三晶体管，其具有用于接收耦合到所述第一和第二晶体管的栅极的参考电流的耦合栅极和漏极以及耦合到所述第一晶体管的源极的源极，其中输出信号由所述第一和第二晶体管的漏极提供， 第一和第二晶体管。 负载耦合到第一和第二晶体管的漏极。 零电流检测器还包括具有耦合在第二晶体管的源极和功率晶体管的第二端子之间的电流通路的第四晶体管和用于接收控制信号的栅极。

公开(公告)号：US20080285638A1

公开(公告)日：2008-11-20

申请号：US12079950

申请日：2008-03-28

Applicant: Yan Liu

Inventor： Yan Liu

IPC: H03H7/30

CPC classification number: H04L25/0216 ,  H04L5/0007 ,  H04L5/0053 ,  H04L5/0094 ,  H04L25/022 ,  H04L25/0232 ,  H04L25/03159 ,  H04L2025/03414 ,  H04L2025/03541

Abstract: A method of estimating a channel response of a channel is provided that includes transforming a frequency domain signal received via the channel into a time domain signal and searching the time domain signal for a location of minimum energy. The method also includes padding the time domain signal with zeroes at the location of minimum energy and transforming the padded time domain signal to a second frequency domain signal. The second frequency domain signal is used as an estimated channel response for the channel.

Abstract translation: 提供一种估计信道的信道响应的方法，包括将经由信道接收的频域信号变换为时域信号，并搜索时域信号以获得最小能量的位置。 该方法还包括以最小能量的位置填充时域信号，并将填充的时域信号变换为第二频域信号。 第二频域信号用作信道的估计信道响应。

公开(公告)号：US20080279314A1

公开(公告)日：2008-11-13

申请号：US12079951

申请日：2008-03-28

Applicant: Yan Liu

Inventor： Yan Liu

IPC: H04L27/06

CPC classification number: H04L27/2657 ,  H04L27/2675 ,  H04L27/2684

Abstract: A method and apparatus for estimating a carrier frequency offset (CFO) in a Digital Radio Mondiale receiver is provided. Orthogonal frequency-division multiplexing (OFDM) demodulation is performed on a received DRM signal to produce OFDM symbols. A cell characteristic in corresponding cells in the OFDM symbols is compared and a carrier index of a frequency pilot cell in the cells is identified based upon the compared cell characteristic. The CFO is estimated based on the identified carrier index of the frequency pilot cell. The ratio of values of the cell characteristic in corresponding cells may be calculated and the frequency pilot cell identified by identifying cells for which the cell characteristic is most nearly equal. The CFO may be estimated by comparing the identified carrier index with an expected carrier index of a frequency pilot cell.

Abstract translation: 提供了一种用于估计数字无线电广播接收机中的载波频率偏移（CFO）的方法和装置。 对接收到的DRM信号进行正交频分复用（OFDM）解调以产生OFDM符号。 比较OFDM符号中的相应小区中的小区特性，并且基于比较的小区特性来识别小区中的频率导频小区的载波索引。 基于识别的频率导频小区的载波指数来估计CFO。 可以计算相应小区中的小区特性的值的比率，并且通过识别小区特性最接近相等的小区来识别频率导频小区。 可以通过将所识别的载波索引与频率导频小区的预期载波索引进行比较来估计CFO。

公开(公告)号：US06891437B2

公开(公告)日：2005-05-10

申请号：US10071013

申请日：2002-02-08

Applicant: Gang Zha ,  Solomon Ng

Inventor： Gang Zha ,  Solomon Ng

IPC: H03F1/34 ,  H03F3/45

CPC classification number: H03F3/45085 ,  H03F1/34 ,  H03F3/45475 ,  H03F2203/45511

Abstract: A circuit structure for performing current amplification. The circuit structure may be standardized as a current amplifier cell such that many types of applications requiring current amplification may be created. The basic amplifier cell, which may accept voltage or current sources as an input signal, produces two identical output signals which may be used for feedback or serve as input to additional amplifier stages. This simple structure may be extended to perform current amplification with variable gain or AC or DC voltage-to-current conversion through the use of appropriately selected resistive elements.

Abstract translation: 一种用于执行电流放大的电路结构。 电路结构可以被标准化为电流放大器单元，使得可以创建需要电流放大的许多类型的应用。 可以接受电压或电流源作为输入信号的基本放大器单元产生两个相同的输出信号，这些信号可用于反馈或用作附加放大器级的输入。 可以通过使用适当选择的电阻元件来扩展这种简单的结构以执行具有可变增益或AC或DC电压到电流转换的电流放大。

公开(公告)号：US20240363501A1

公开(公告)日：2024-10-31

申请号：US18634663

申请日：2024-04-12

Applicant: Shenzhen STS Microelectronics Co., Ltd ,  STMicroelectronics International N.V.

Inventor： Qian LIU ,  Roberto TIZIANI

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/49562 ,  H01L23/3675 ,  H01L23/49531 ,  H01L24/29 ,  H01L24/37 ,  H01L25/0652 ,  H01L2224/29005 ,  H01L2224/29022 ,  H01L2224/3702 ,  H01L2224/37147 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/13091

Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source. The semiconductor package further comprises a second conductive level comprising a gate lead-out portion electrically connected with the gate connection portion and a source lead-out portion electrically connected with the source connection portion, wherein the first conductive level is positioned between the second conductive level and the chip level. Embodiments of the present disclosure may enhance the working performance of the product by improving consistency of conductive paths from the gate and the source of each power transistor to corresponding points.

公开(公告)号：US20240203843A1

公开(公告)日：2024-06-20

申请号：US18532950

申请日：2023-12-07

Applicant: SHENZHEN STS MICROELECTRONICS CO., LTD.

Inventor： Lin LIANG ,  Qiao CHEN ,  Junjie QIU ,  Yi Ming LIANG

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49568 ,  H01L23/49527 ,  H01L23/49575 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0652 ,  H01L2224/16137 ,  H01L2224/16225 ,  H01L2224/32235 ,  H01L2224/32245 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/1306

Abstract: A semiconductor package is provided, including a package forming method and a power supply module. The semiconductor package may include a first chip comprising a first surface, and a second surface opposite the first surface. The semiconductor package may also include a chip interconnect component located on the second surface of the first chip. In addition, the semiconductor package may include a second chip located on the chip interconnect component, comprising a third surface in contact with the chip interconnect component, and a fourth surface opposite the third surface. The chip interconnect component comprises an electrically conductive frame, one side of the electrically conductive frame is electrically connected to the second surface of the first chip, and the other side of the electrically conductive frame is electrically connected to the third surface of the second chip. The chip interconnect component may further comprise an insulating material for filling a gap of the electrically conductive frame between the first chip and the second chip. By arranging at least two chip on both sides of a preformed chip interconnect component, embodiments of the present disclosure achieve a high density chip layout for a 3D structure.

公开(公告)号：US08194761B2

公开(公告)日：2012-06-05

申请号：US12079937

申请日：2008-03-28

Applicant: Yan Liu

Inventor： Yan Liu

IPC: H04L27/28

CPC classification number: H04L27/2657 ,  H04L27/2675

Abstract: A system and method for estimating sample clock frequency offset (εs) in a digital radio mondiale (DRM) system such as, for example, DRM receivers. The system and method includes using a relationship given by the following equation: ɛ s = linearfit ( angle ⁢ ( P G m P G ⁢ _ ⁢ tr m P G m ⁢ - ⁢ cycle P G ⁢ _ ⁢ tr m ⁢ - ⁢ cycle ) , l ) × N 2 ⁢ π × cycle × ( N + L ) wherein the PGm is the gain pilot received in the mth symbol and PG—trm is the gain pilot transmitted in the mth symbol, the PGm-cycle is the gain pilot received in (m-cycle)th symbol, the PG—trm-cycle is the second gain pilot transmitted in (m-cycle)th symbol, the l is the index of the sub-carrier associated with the gain pilot, the N is a factor of a sample point number of a useful symbol, the L is a sample point number of a guard interval, and the cycle is the interval of two symbols which are inserted gain pilots at the same sub-carriers (l).

Abstract translation: 用于估计数字无线电台（DRM）系统（例如DRM接收机）中的采样时钟频率偏移（＆egr）的系统和方法。 该系统和方法包括使用由以下等式给出的关系：εε= linearfit（角度（PG m PG _ trm PG m-周期PG _trm-周期），l） ×N 2＆pgr; ×周期×（N + L）其中PGm是在第m个符号中接收的增益导数，PG-trm是在第m个符号中发送的增益导数，PGm周期是以（m-周期）th 符号，PG-trm周期是以（m周期）符号发送的第二增益导频，l是与增益导频相关联的子载波的索引，N是采样点数的因子 一个有用的符号，L是保护间隔的采样点数，周期是在相同子载波（l）处插入增益导频的两个符号的间隔。

公开(公告)号：US07714561B2

公开(公告)日：2010-05-11

申请号：US12254718

申请日：2008-10-20

Applicant: Weiguo Ge ,  Wangsheng Xie ,  Guojun Li ,  Matteo Traldi

Inventor： Weiguo Ge ,  Wangsheng Xie ,  Guojun Li ,  Matteo Traldi

IPC: G05F1/00

CPC classification number: H02M3/156 ,  H02M3/33507

Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

Abstract translation: 用于DC-DC转换器的驱动器，其可以利用反激式或降压 - 升压转换器电路。 驱动器包括驱动电路和接口电路。 接口电路具有感测来自直流电源的输入电压并且向驱动器选择器产生传感器信号的传感器。 驱动器选择器将传感器信号与比较电压进行比较以确定转换器电路的类型，然后将选择器信号发送到用于控制驱动器电路的一个或多个部件的驱动器电路，例如逻辑电路 用于驱动转换器来调节转换器输出。 传感器包括检测电阻器以及电流检测放大器，其适于连接到电源的高侧或低侧，同时仍然产生基本相等的输出电压或传感器信号。

公开(公告)号：US07573246B2

公开(公告)日：2009-08-11

申请号：US11684434

申请日：2007-03-09

Applicant: DaSong Lin ,  Gang Zha

Inventor： DaSong Lin ,  Gang Zha

IPC: G05F1/575 ,  G05F3/26

CPC classification number: G05F1/575

Abstract: A compensated regulator includes a transconductance stage having a positive input for receiving a reference voltage, a negative input, and an output, an adjustable compensation block coupled between the output of the transconductance stage and ground, a feedback circuit having a first node coupled to the output of the compensated regulator, a second node coupled to the negative input of the transconductance stage, and a third node coupled to ground, and a driver stage having an input coupled to the output of the transconductance stage, a current output coupled to the output of the compensated regulator, and a sense output coupled to the adjustable compensation block.

Abstract translation: 补偿稳压器包括跨导级，其具有用于接收参考电压的正输入端，负输入端和输出端，耦合在跨导级与地的输出之间的可调补偿块，具有耦合到 补偿调节器的输出，耦合到跨导级的负输入的第二节点和耦合到地的第三节点，以及具有耦合到跨导级的输出的输入的驱动级，耦合到输出的电流输出 并且耦合到可调补偿块的感测输出。

公开(公告)号：US07496720B2

公开(公告)日：2009-02-24

申请号：US11713340

申请日：2007-03-02

Applicant: Lijun Tian

Inventor： Lijun Tian

IPC: G06F12/00

CPC classification number: H04B14/04

Abstract: A micro-controller is connected between a hardware-based adaptive differential pulse code modulation (ADPCM) decoder and a read only memory (ROM) storing both micro-controller programming instructions and ADPCM encoded source file data. A micro-controller architecture implements time multiplexed ROM addressing driven by a two phase clock signal. In an instruction phase, a program counter supplies ROM address(es) for retrieving micro-controller programming instructions. In a decoder phase, an address counter supplies ROM address(es) for retrieving portions of the ADPCM encoded source file data. ADPCM encoded source file data extracted from the ROM in the decoder phase of the clock signal is delivered to the decoder for processing during the subsequent instruction phase of the clock signal. The selection between program counter and address counter supplied addresses for application to the ROM is made by a two phase clock signal driven multiplexer.

Abstract translation: 微控制器连接在基于硬件的自适应差分脉码调制（ADPCM）解码器和存储微控制器编程指令和ADPCM编码的源文件数据的只读存储器（ROM）之间。 微控制器架构实现由两相时钟信号驱动的时间复用ROM寻址。 在指令阶段，程序计数器提供用于检索微控制器编程指令的ROM地址。 在解码器阶段，地址计数器提供用于检索ADPCM编码的源文件数据的部分的ROM地址。 在时钟信号的解码器相位中从ROM提取的ADPCM编码的源文件数据被传送到解码器，以在时钟信号的后续指令阶段进行处理。 应用于ROM的程序计数器和地址计数器提供的地址之间的选择由两相时钟信号驱动的多路复用器进行。