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公开(公告)号：US11431342B2
公开(公告)日：2022-08-30
申请号：US17521210
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Gagan Midha , Kallol Chatterjee , Anand Kumar , Ankit Gupta
Abstract: A PLL includes an input comparison circuit comparing a reference signal to a divided feedback signal to thereby control a charge pump that generates a charge pump output signal. A filter receives the charge pump output signal when a switch is closed, and produces an oscillator control signal causing an oscillator to generate an output signal. Divider circuitry divides the output signal by a divisor to produce the divided feedback signal. Divisor generation circuitry changes the divisor over time so the output signal ramps from a start frequency to an end frequency. Modification circuitry stores a first oscillator control signal equal to the value of the oscillator control signal when the frequency of the output signal is the start ramp frequency. When the frequency of the output signal reaches the end ramp frequency, the switch is opened, and the stored first oscillator control signal is applied to the loop filter.
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公开(公告)号：US11429478B2
公开(公告)日：2022-08-30
申请号：US16867325
申请日：2020-05-05
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Jain
Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.
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公开(公告)号：US20220269410A1
公开(公告)日：2022-08-25
申请号：US17742987
申请日：2022-05-12
Inventor： Nitin CHAWLA , Giuseppe DESOLI , Anuj GROVER , Thomas BOESCH , Surinder Pal SINGH , Manuj AYODHYAWASI
Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
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公开(公告)号：US11418204B2
公开(公告)日：2022-08-16
申请号：US17519122
申请日：2021-11-04
Applicant: STMicroelectronics International N.V.
Inventor： Ankit Gupta
Abstract: A calibration scheme is used to control PLL bandwidth and contain its spread. In open loop, the VCO control voltage is swept over a range of values and VCO output frequency is measured at each control voltage level. The gain KVCO is determined for each measured output frequency and a corresponding current magnitude for the variable magnitude charge pump is calculated from a ratio of a constant to the gain KVCO and correlated in a look-up table to the measured output frequency. Once calibration is completed, the PLL loop is closed and a calculated current magnitude is fetched from the look-up table based on a desired output frequency for the PLL circuit. The variable magnitude charge pump circuit is then controlled to generate a charge pump current with a magnitude corresponding to the fetched charge pump current magnitude.
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公开(公告)号：US20220244308A1
公开(公告)日：2022-08-04
申请号：US17164570
申请日：2021-02-01
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Shiv Kumar Vats , Tripti Gupta
IPC: G01R31/3177 , G06F1/04 , G01R31/317
Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.
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Patent Agency Ranking
公开(公告)号：US20220229752A1
公开(公告)日：2022-07-21
申请号：US17152901
申请日：2021-01-20
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal
IPC: G06F11/263 , G06F11/22 , G06F1/06
Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
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公开(公告)号：US11374580B2
公开(公告)日：2022-06-28
申请号：US17381754
申请日：2021-07-21
Applicant: STMicroelectronics International N.V.
Inventor： Sagnik Mukherjee , Ankit Gupta
Abstract: A PLL includes a phase-frequency-detector-and-charge-pump-circuit (PFDCPC) receiving a reference signal and divided signal, and generating a charge-pump current. A loop-filter is between output of the PFDCPC and a reference-voltage. A first voltage-to-current converter (V2I1) has low gain, and a second voltage-to-current converter (V2I2) has high gain. A low-gain-path is between outputs of the PFDCPC and V2I1, and a high-gain-path is between the outputs of the PFDCPC and V2I2. A current-controlled-oscillator receives an input signal, and generates an output signal. A loop divider divides the output signal by a divider-value, producing the divided signal. The low-gain-path runs directly from the PFDCPC, through the V2I1, to the input of the current-controlled-oscillator. The high-gain-path runs from the PFDCPC to the loop-filter, from a tap of the loop-filter to a low-pass filter through a current mirror, from a tap of the low-pass filter through the V2I2, to the input of the current-controlled-oscillator.
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公开(公告)号：US20220196485A1
公开(公告)日：2022-06-23
申请号：US17521123
申请日：2021-11-08
Applicant: STMicroelectronics International N.V.
Inventor： Pijush Kanti PANJA , Kallol CHATTERJEE , Atul DWIVEDI
Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ΔVbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ΔVbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.
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公开(公告)号：US11360143B2
公开(公告)日：2022-06-14
申请号：US17083876
申请日：2020-10-29
Applicant: STMicroelectronics International N.V. , STMicroelectronics Application GmbH , STMicroelectronics S.r.l.
Inventor： Avneep Kumar Goyal , Deepak Baranwal , Thomas Szurmant , Nicolas Bernard Grossier
IPC: G01R31/317 , G01R31/3185 , G01R31/3193 , G06F11/34 , G01R31/319 , G06F11/36
Abstract: A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.
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公开(公告)号：US11356018B2
公开(公告)日：2022-06-07
申请号：US17313533
申请日：2021-05-06
Applicant: STMicroelectronics International N.V.
Inventor： Vikas Rana
IPC: H02M3/07
Abstract: A charge pump includes an intermediate node capacitively coupled to receive a first clock signal oscillating between a ground and positive supply voltage, the intermediate node generating a first signal oscillating between a first and second voltage. A level shifting circuit shifts the first signal in response to a second clock signal to generate a second signal oscillating between first and third voltages. A CMOS switching circuit includes a first transistor having a source coupled to an input, a second transistor having a source coupled to an output and a gate coupled to receive the second signal. A common drain of the CMOS switching circuit is capacitively coupled to receive the first clock signal. When positively pumping, the first voltage is twice the second voltage and the third voltage is ground. When negatively pumping, the first and third voltages are of opposite polarity and the second voltage is ground.
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