公开(公告)号：US10381054B1

公开(公告)日：2019-08-13

申请号：US15906588

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dhani Reddy Sreenivasula Reddy ,  Vinay Bhat Soori

IPC: G11C7/00 ,  G11C7/12 ,  G11C5/14 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/419

Abstract: The present disclosure relates to a structure which includes an assist circuit which is configured to add a boost voltage using a common boost logic device for both a read logic circuit and a write logic circuit of the assist circuit.

公开(公告)号：US20190244954A1

公开(公告)日：2019-08-08

申请号：US15889635

申请日：2018-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahadeva Iyer Natarajan ,  Haojun Zhang ,  Chien-Hsin Lee

IPC: H01L27/02 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/0292 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53238

Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.

公开(公告)号：US10374064B2

公开(公告)日：2019-08-06

申请号：US15901447

申请日：2018-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/225 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165

Abstract: A method of forming semiconductor devices that includes forming an oxide that is doped with a punch through dopant on a surface of a first semiconductor material having a first lattice dimension, and diffusing punch through dopant from the oxide into the semiconductor material to provide a punch through stop region. The oxide may then be removed. A second semiconductor material may be formed having a second lattice dimension on the first semiconductor material having the first lattice dimension. A difference between the first lattice dimension and the second lattice dimension forms a strain in the second semiconductor material. A gate structure and source and drain regions are formed on the second semiconductor material.

公开(公告)号：US20190237363A1

公开(公告)日：2019-08-01

申请号：US15882291

申请日：2018-01-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jinsheng GAO ,  Daniel JAEGER ,  Chih-Chiang CHANG ,  Michael AQUILINO ,  Patrick CARPENTER ,  Junsic HONG ,  Mitchell RUTKOWSKI ,  Haigou HUANG ,  Huy CAO

IPC: H01L21/768 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a cap structure and methods of manufacture. The structure includes: a gate structure composed of conductive gate material; sidewall spacers on the gate structure, extending above the conductive gate material; and a capping material on the conductive gate material and extending over the sidewall spacers on the gate structure.

公开(公告)号：US10366931B2

公开(公告)日：2019-07-30

申请号：US16133850

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Cheng Chi ,  Pietro Montanini ,  Tenko Yamashita ,  Nicolas Loubet

IPC: H01L29/76 ,  H01L21/8238 ,  H01L27/092

Abstract: This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.

公开(公告)号：US10366919B2

公开(公告)日：2019-07-30

申请号：US15709956

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. Licausi ,  Xunyuan Zhang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3213

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

公开(公告)号：US20190229207A1

公开(公告)日：2019-07-25

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/761

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US20190229184A1

公开(公告)日：2019-07-25

申请号：US15876530

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Cameron Luce ,  Pernell Dongmo

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

公开(公告)号：US20190229183A1

公开(公告)日：2019-07-25

申请号：US15875132

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting WANG ,  Hui ZANG ,  Chun Yu WONG ,  Kwan-Yong LIM

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762

Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.

公开(公告)号：US20190228976A1

公开(公告)日：2019-07-25

申请号：US15876407

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Jinsheng GAO ,  Hong YU ,  Jinping LIU ,  Huang LIU

IPC: H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to capping structures and methods of manufacture. The structure includes: a plurality of gate structures in a first location with a first density; a plurality of gate structures in a second location with a second density different than the first density; and a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location.