公开(公告)号：US20190181040A1

公开(公告)日：2019-06-13

申请号：US15834151

申请日：2017-12-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Minghao Tang ,  Rui Chen ,  Yuping Ren

IPC: H01L21/768 ,  H01L21/033

Abstract: Methods of fabricating an interconnect structure. A first sacrificial layer is deposited over a dielectric layer, and a block mask is formed that covers an area on the first sacrificial layer. A second sacrificial layer is deposited over the block mask and the first sacrificial layer. After the block mask is formed, the second sacrificial layer is patterned to form a mandrel that is arranged in part on a portion of the block mask.

公开(公告)号：US10319827B2

公开(公告)日：2019-06-11

申请号：US15647403

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Nigel Chan

IPC: H01L29/51 ,  H01L29/165 ,  H01L29/66

Abstract: A high voltage transistor may be formed on the basis of well-established CMOS techniques by using a buried insulating material of an SOI architecture as gate dielectric material, while the gate electrode material may be provided in the form of a doped semiconductor region positioned below the buried insulating layer. The high voltage transistor may be formed with high process compatibility on the basis of a process flow for forming sophisticated fully depleted SOI transistors, wherein, in some illustrative embodiments, the high voltage transistor may also be provided as a fully depleted transistor configuration.

公开(公告)号：US10319732B2

公开(公告)日：2019-06-11

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66 ,  H01L21/84 ,  H01L29/786

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US10319627B2

公开(公告)日：2019-06-11

申请号：US15376831

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/66

Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

公开(公告)号：US10312356B1

公开(公告)日：2019-06-04

申请号：US16013363

申请日：2018-06-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qizhi Liu ,  Vibhor Jain ,  James W. Adkisson ,  Sarah McTaggart ,  Mark Levy

IPC: H01L31/0328 ,  H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/265

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are arranged to surround a plurality of active regions, and a collector is located in each of the active regions. A base layer includes a plurality of first sections that are respectively arranged over the active regions and a plurality of second sections that are respectively arranged over the trench isolation regions. The first sections of the base layer contain single-crystal semiconductor material, and the second sections of the base layer contain polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a plurality of cavities. A plurality of emitter fingers are respectively arranged on the first sections of the base layer.

公开(公告)号：US10304763B2

公开(公告)日：2019-05-28

申请号：US15858673

申请日：2017-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Richard S. Graf ,  Sudeep Mandal ,  Kibby Horsford

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

Abstract: A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a mold with an active side of each die facing a surface of the mold; placing a leadframe strip on the mold, wherein the leadframe strip includes etched and half etched portions positioned between each die; placing a mold cover over the mold and dies; and adding mold compound in spaces between the dies and mold cover.

公开(公告)号：US20190157213A1

公开(公告)日：2019-05-23

申请号：US15817801

申请日：2017-11-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ronald NAUMANN ,  Matthias ZINKE ,  Robert SEIDEL ,  Tobais BARCHEWITZ

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor structure with a substantially straight contact profile and methods of manufacture. The structure includes a block material comprising an upper oxidized layer at an interface with an insulating material; and an interconnect contact structure with a substantially straight profile through the oxidized layer of the block material.

公开(公告)号：US10298345B2

公开(公告)日：2019-05-21

申请号：US15406350

申请日：2017-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kai Yang ,  Bin Sun ,  Yuan Yao ,  Zhen Han

IPC: H04J3/06

Abstract: Aspects of the present disclosure includes a method and program product for clock synchronization of a networked computer system. The method records a time (t1) when a first codeword marker in a datastream is sent from a master computer to a slave computer and records a second time (t2) when the slave computer receives the first codeword marker. The method includes recording a third time (t3) when a third codeword marker in a datastream is sent from the slave computer to the master computer. The method includes recording a fourth time t4 when the master receives the third codeword marker from the slave. The method calculates a time offset θ, according to; θ = ( t ⁢ ⁢ 2 - t ⁢ ⁢ 1 ) + ( t ⁢ ⁢ 4 - t ⁢ ⁢ 3 ) 2 , and a roundtrip delay δ, according to δ=(t4−t1)−(t3−t2). The clock in the slave computer is synchronized with a clock in the master computer using θ and δ.

公开(公告)号：US10297675B1

公开(公告)日：2019-05-21

申请号：US15795879

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alina Vinslava ,  Hsien-Ching Lo ,  Yongjun Shi ,  Jianwei Peng ,  Jianghu Yan ,  Yi Qi

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.

公开(公告)号：US10297664B2

公开(公告)日：2019-05-21

申请号：US15486351

申请日：2017-04-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/165 ,  H01L29/08

Abstract: A method of forming nanosheet and nanowire transistors includes the formation of alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si), where the germanium content within respective layers of the silicon germanium is systemically varied in order to mediate the selective etching of these layers. The germanium content can be controlled such that voids created by removal of the silicon germanium have uniform dimensions, and the backfilling of such voids with gate dielectric and gate conductor layers proximate to silicon nanosheets or nanowires results in devices having a uniform effective gate length.