公开(公告)号：US07138317B2

公开(公告)日：2006-11-21

申请号：US10831874

申请日：2004-04-26

Applicant: Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

Inventor： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC: H01L21/8234

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

Abstract translation: 在由衬底上的STI隔离区隔开的有源区上形成多个栅极氧化物厚度的方法。 将第一层氧化物生长至约50埃的厚度，然后除去选定的区域。 生长比第一生长氧化物薄的第二层氧化物。 对于三种不同的栅极氧化物厚度，选择的第二氧化物生长区域用N 2 O 3等离子体氮化，这增加了栅极氧化物的介电常数并降低了有效的氧化物厚度。 为了实现四种不同的栅极氧化物厚度，对所选择的第一生长氧化物和选择的第二生长氧化物区域进行氮化。 栅极氧化物的氮化还防止杂质掺杂剂跨过栅极氧化物层迁移并减少待机电流的泄漏。 该方法还减少由HF蚀刻剂引起的STI区域的拐角损失。

公开(公告)号：US20060183279A1

公开(公告)日：2006-08-17

申请号：US11279016

申请日：2006-04-07

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

Abstract translation: 一种具有改善的电荷迁移率的应变通道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

公开(公告)号：US07052946B2

公开(公告)日：2006-05-30

申请号：US10798960

申请日：2004-03-10

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

公开(公告)号：US20060014396A1

公开(公告)日：2006-01-19

申请号：US10892014

申请日：2004-07-14

Applicant: Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Ju-Wang Hsu ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/302 ,  H01L21/31

CPC classification number: H01L21/31111 ,  H01L21/823481 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78

Abstract: A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.

Abstract translation: 在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。 在半导体衬底上形成隔离结构。 在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。 形成光致抗蚀剂掩模以部分覆盖原始氮化物层。 执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。 因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

公开(公告)号：US20050214998A1

公开(公告)日：2005-09-29

申请号：US10810795

申请日：2004-03-26

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/8238

CPC classification number: H01L21/76829 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

Abstract: A semiconductor device and method for forming the same for improving charge mobility in NMOS and PMOS devices simultaneously, the method including forming a first dielectric layer including a stress type selected from the group consisting of tensile stress and compressive stress over the respective PMOS and NMOS device regions; removing a portion of the first dielectric layer overlying one of the PMOS and NMOS device regions; forming a second dielectric layer including a stress type opposite from the first dielectric layer stress type over the respective PMOS and NMOS device regions; and, removing a portion of the second dielectric layer overlying one of the PMOS and NMOS device regions having an underlying first dielectric layer to form a compressive stress dielectric layer over the PMOS device region and a tensile stress dielectric layer over the NMOS device region.

Abstract translation: 一种半导体器件及其制造方法，用于同时改善NMOS和PMOS器件的电荷迁移率，该方法包括形成第一介电层，该第一介电层包括在相应的PMOS和NMOS器件上包括拉应力和压应力的应力类型 区域; 去除覆盖所述PMOS和NMOS器件区域中的一个的所述第一电介质层的一部分; 在相应的PMOS和NMOS器件区域上形成包括与第一介电层应力型相反的应力类型的第二介质层; 以及去除覆盖具有下面的第一介电层的PMOS器件区域和NMOS器件区域之一的第二介电层的一部分，以在PMOS器件区域上形成压应力介电层，并在NMOS器件区域上形成拉伸应力介电层。

公开(公告)号：US20050199958A1

公开(公告)日：2005-09-15

申请号：US10798960

申请日：2004-03-10

Applicant: Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Lin Chen ,  Ju-Wang Hsu ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A strained channel MOSFET device with improved charge mobility and method for forming the same, the method including providing a first gate with a first semiconductor conductive type and second gate with a semiconductor conductive type on a substrate; forming a first strained layer with a first type of stress on said first gate; and, forming a second strained layer with a second type of stress on said second gate.

Abstract translation: 一种具有改善的电荷迁移率的应变沟道MOSFET器件及其形成方法，所述方法包括在衬底上提供具有半导体导电类型的第一半导体导电类型的第一栅极和第二栅极; 在所述第一栅极上形成具有第一类型应力的第一应变层; 并且在所述第二浇口上形成具有第二类型应力的第二应变层。

公开(公告)号：US06861339B2

公开(公告)日：2005-03-01

申请号：US10274570

申请日：2002-10-21

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/30 ,  H01L29/49 ,  H01L29/78 ,  H01L21/26

CPC classification number: H01L21/02532 ,  H01L21/02595 ,  H01L21/2022 ,  H01L21/28035 ,  H01L21/3003 ,  H01L29/4925 ,  H01L29/78

Abstract: Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance.

Abstract translation: 在形成硅层的方法中，使用由较高结晶硅材料形成的至少一个子层和由下部结晶硅材料形成的至少一个子层。 使用较高结晶硅材料的氢处理形成下部结晶硅材料。 该方法对于形成具有增强尺寸控制和增强性能的多晶硅基栅电极特别有用。

公开(公告)号：US06780741B2

公开(公告)日：2004-08-24

申请号：US10338155

申请日：2003-01-08

Applicant: Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC: H01L213205

CPC classification number: H01L21/28044 ,  H01L29/4925

Abstract: A method of fabricating a gate structure for a MOSFET device, allowing a reduced polysilicon depletion effect as well as increased carrier mobility to be realized, has been developed. The method features a polysilicon-germanium component of the gate structure, sandwiched between an underlying polysilicon seed layer and an overlying polysilicon cap layer. The inclusion of germanium in the deposited polysilicon-germanium component results in enhanced dopant activation and thus a reduced polysilicon depletion effect. The polysilicon seed and cap layers are subjected to low temperature, anneal procedures, performed in situ in a hydrogen ambient, after deposition of the polysilicon layers. The in situ anneal procedures alters the columnar grains of the polysilicon layers to small, random grains resulting in smooth polysilicon surfaces, with the smooth surface of the polysilicon seed layer interfacing the underlying gate insulator layer resulting in enhanced carrier mobility when compared to counterpart polysilicon seed layer comprised with rough surfaces.

Abstract translation: 已经开发了制造用于MOSFET器件的栅极结构的方法，其允许减少的多晶硅耗尽效应以及增加的载流子迁移率被实现。 该方法具有栅极结构的多晶硅 - 锗组分，夹在下面的多晶硅种子层和上覆多晶硅覆盖层之间。 在沉积的多晶硅 - 锗组分中包含锗导致增强的掺杂剂活化，从而减少了多晶硅的耗尽效应。 多晶硅种子和盖层经过低温退火处理，在沉积多晶硅层之后在氢环境中原位进行。 原位退火程序将多晶硅层的柱状晶体改变成小的随机晶粒，产生平滑的多晶硅表面，与对应的多晶硅晶粒相比，多晶硅籽晶层的平滑表面与下面的栅极绝缘体层相接触，导致增强的载流子迁移率 层包含粗糙表面。

公开(公告)号：US10683978B2

公开(公告)日：2020-06-16

申请号：US16001920

申请日：2018-06-06

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: F21S8/04 ,  F21K9/20 ,  F21V19/00 ,  F21S8/00 ,  F21V3/02 ,  F21Y105/18 ,  F21Y115/10 ,  F21V21/002 ,  H01R33/94 ,  H02G3/20 ,  H01R33/46 ,  F16M13/02

Abstract: A lamp power assembling structure and method, the lamp power assembling structure is installed indoors and is connected an indoor power source, and includes a lamp power seat and a lamp fixing seat. The lamp power seat has a first power connector for connecting to the indoor power source and two sliding trenches. Each sliding trench has an arced channel and an enlarged hole formed at an end of the arced channel. The lamp fixing seat has a second power connector corresponding to the first power connector and two fasteners separately corresponding to the two enlarged holes. The two fasteners are separately inserted into the two enlarged holes, and the lamp fixing seat is rotated about the first and second power connectors so as to make the two fasteners separately to be engaged with the arced channels to fix the lamp fixing seat to the lamp power seat.

公开(公告)号：US20190022835A1

公开(公告)日：2019-01-24

申请号：US16143413

申请日：2018-09-26

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: B25B23/12 ,  B25B13/06 ,  B25B23/00

Abstract: A socket contains: a body, a push member, and a reverse pushing structure. The body includes a connecting section and a fitting section, the connecting section has a first polygonal orifice configured to accommodate a socket wrench, and the fitting section has a second polygonal orifice for driving a fastener element. The body includes a receiving groove defined therein communicating with the second polygonal orifice, and the push member is movably accommodated in the second polygonal orifice and includes at least one magnetic attraction element. The reverse pushing structure is housed in the receiving groove and configured to push the push member toward the rim of the second polygonal orifice.