公开(公告)号：US12266649B2

公开(公告)日：2025-04-01

申请号：US17743044

申请日：2022-05-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wu-Der Yang

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

公开(公告)号：US12266600B2

公开(公告)日：2025-04-01

申请号：US17685511

申请日：2022-03-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/522 ,  H01L23/544

Abstract: The present application discloses a semiconductor device with a decoupling unit. The semiconductor device includes a first tier structure including conductive features of positioned over a substrate, and a decoupling unit the first tier structure positioned between the conductive features; a first-tier-alignment mark positioned on the decoupling unit, and including a fluorescence material; a second tier structure positioned on the first tier structure and including conductive features positioned over and deviated from the conductive features of the first tier structure, and a decoupling unit of positioned over the first tier structure, and positioned between the conductive features of the second tier structure; and a second-tier-alignment mark positioned on the decoupling unit of the second tier structure, and including a fluorescence material. The decoupling units include a low-k dielectric material and respectively include a bottle-shaped cross-sectional profile.

公开(公告)号：US20250105214A1

公开(公告)日：2025-03-27

申请号：US18514089

申请日：2023-11-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

Abstract: An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.

公开(公告)号：US12262524B2

公开(公告)日：2025-03-25

申请号：US17555758

申请日：2021-12-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Jung-Yu Wu

IPC: H10B12/00

Abstract: The present application provides a method for manufacturing a memory device having word lines with improved resistance, and a manufacturing method of the memory device. The method includes providing a semiconductor substrate defined with a peripheral region and an array region at least partially surrounded by the peripheral region; forming a first recess extending into the semiconductor substrate and disposed in the array region; and forming a word line disposed within the first recess. The formation of the word line includes disposing an insulating layer conformal to the first recess, and forming a conductive member surrounded by the insulating layer and having a second recess extending into the conductive member and toward the semiconductor substrate.

公开(公告)号：US12259417B2

公开(公告)日：2025-03-25

申请号：US18407477

申请日：2024-01-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Mei Chuan Peng

IPC: G01R27/08 ,  G01R27/14 ,  G01R31/52 ,  G01R31/74

Abstract: A method of measuring a fuse resistance includes steps as follows. A predetermined voltage value of a force voltage on a common ground (CGND) bus electrically connected to at least one fuse element, a first current value of a measured current through the CGND bus in a first condition, and a second current value of another measured current through the CGND bus in a second condition are preloaded. The second current value is subtracted from the first current value, so as to get a subtracted current value, thereby removing a value of a leakage current through the CGND bus. The predetermined voltage value is divided by the subtracted current value to equal the fuse resistance of the at least one fuse element.

公开(公告)号：US20250098151A1

公开(公告)日：2025-03-20

申请号：US18370490

申请日：2023-09-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WEI-CHUAN FANG

IPC: H10B12/00

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a landing pad, and air gap protection structure. The bit line is disposed on the substrate. The isolation spacer is disposed on a side of the bit line. The isolation spacer includes an air gap. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure has an upper portion above a top surface of the landing pad and a lower portion below the upper portion. A ratio between a thickness of the lower portion and a thickness of the upper portion is greater than 0.6 and less than 0.8.

公开(公告)号：US20250098150A1

公开(公告)日：2025-03-20

申请号：US18369144

申请日：2023-09-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kai-Po SHANG

IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

Abstract: Embodiments of this disclosure provide a method of manufacturing a semiconductor structure. The method includes the following steps. A substrate including active areas and insulation areas between the active areas is provided. A plurality of bit line structures are formed on a top surface of the substrate. A first oxide layer is deposited on each of the bit line structures. A spacer structure is deposited on the first oxide layer. Besides, the spacer structure is a multilayer structure and includes a second oxide layer. The first oxide layer and second oxide layer are removed to form a first air gap and a second air gap as a spacer. A plurality of landing pads is formed over the plurality of bit line structures and the first air gap and the second air gap. In addition, a semiconductor structure is also provided in this disclosure.

公开(公告)号：US20250096048A1

公开(公告)日：2025-03-20

申请号：US18961486

申请日：2024-11-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin SHIH ,  Hsueh-Han LU ,  Yu-Ting LIN

IPC: H01L21/66 ,  H10B12/00

Abstract: A test structure for use in a dynamic random access memory is provided. A first gate structure is disposed in a semiconductor substrate. First and second source/drain regions are disposed in the semiconductor substrate and at two sides of the first gate structure. A bit line structure is disposed on the first source/drain region. A dielectric layer is disposed on the semiconductor substrate. First and second landing pads are disposed on the dielectric layer. A first contact plug is disposed in the dielectric layer and is electrically connected to the second source/drain region and the first landing pad. A conductive layer is disposed on and electrically connected to the first landing pad and the second landing pad, in which the conductive layer covers upper surfaces of the first and second landing pads and has a portion between the first landing pad and the second landing pad.

公开(公告)号：US12256565B2

公开(公告)日：2025-03-18

申请号：US18636545

申请日：2024-04-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kuo-Hui Su

IPC: H10D64/01 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H10D64/27 ,  H10D64/68

Abstract: A method for preparing a recessed gate structure includes forming a recessed structure, wherein the recessed structure includes a substrate with the recess extending into the substrate from a topmost surface of the substrate; forming a first functional layer to at least cover a sidewall of a recess of the recessed structure; forming a second functional layer to cover the first functional layer; performing a rapid thermal treatment to form an interfacial layer extending along an interface between the first functional layer and the second functional layer; and forming a conductive feature to fill up the recess.

公开(公告)号：US12255146B2

公开(公告)日：2025-03-18

申请号：US18208495

申请日：2023-06-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an interconnection structure, a first isolation feature, and a second isolation feature. The interconnection structure has a first lateral surface and a second lateral surface. The first isolation feature is disposed on the first lateral surface of the interconnection structure. The second isolation feature is disposed on the second lateral surface of the interconnection structure. The first isolation feature is different from the second isolation feature.