公开(公告)号：US20100322414A1

公开(公告)日：2010-12-23

申请号：US12868874

申请日：2010-08-26

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L9/28

CPC classification number: H04L25/03866

Abstract: Ternary (3-value) and higher, multi-value digital scramblers/descramblers in digital communications. The method and apparatus of the present invention includes the creation of ternary (3-value) and higher value truth tables that establish ternary and higher value scrambling functions which are its own descrambling functions. The invention directly codes by scrambling ternary and higher-value digital signals and directly decodes by descrambling with the same function. A disclosed application of the invention is the creation of composite ternary and higher-value scrambling devices and methods consisting of single scrambling devices or functions combined with ternary or higher value shift registers. Another disclosed application is the creation of ternary and higher-value spread spectrum digital signals. Another disclosed application is a composite ternary or higher value scrambling system, comprising an odd number of scrambling functions and the ability to be its own descrambler.

Abstract translation: 三值（3值）以上，多值数字加扰/解码器在数字通信。 本发明的方法和装置包括创建三值（3值）和更高价值的真值表，其建立作为它自己的解扰功能的三值和更高值的加扰函数。 本发明通过对三进制数值信号进行加扰直接编码，并通过相同功能的解扰直接解码。 本发明的公开的应用是创建由单个扰码设备或与三元或更高值移位寄存器组合的功能组成的复合三元和更高值的加扰设备和方法。 另一个公开的应用是创建三值和更高价值的扩频数字信号。 另一个公开的应用是复合三元或更高值的加扰系统，其包括奇数个加扰功能以及作为其自己的解扰器的能力。

公开(公告)号：US07656196B2

公开(公告)日：2010-02-02

申请号：US12061286

申请日：2008-04-02

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03K19/00

CPC classification number: G06F7/49 ,  G06F17/5045 ,  G11C11/56 ,  H03K19/0002

Abstract: N-valued re-circulating latches using n-valued reversible inverters with n>3 are disclosed. Latches using n-valued self-reversing inverters are provided; latches using n-valued universal inverters are provided; and latches using inverters which are not self-reversing or universal are also provided. A latch may use two individually controlled gates. It may also use one individually controlled gate. N-valued latches are provided wherein a state is represented by a signal being an independent instance of a physical phenomenon. A latch not using absence-of-signal as a state is also provided.

Abstract translation: 公开了使用n值大于3的n值可逆逆变器的N值再循环锁存器。 提供使用n值自逆变换器的锁存器; 提供使用n值通用逆变器的锁存器; 并且还提供使用不是自反转或通用的逆变器的锁存器。 闩锁可以使用两个单独控制的门。 它也可以使用一个单独控制的门。 提供了N值锁存器，其中状态由作为物理现象的独立实例的信号表示。 还提供了不使用不存在信号作为状态的锁存器。

公开(公告)号：US07643632B2

公开(公告)日：2010-01-05

申请号：US10935960

申请日：2004-09-08

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L9/00

CPC classification number: H03K19/20

Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Abstract translation: 公开了通过应用多值逆变器创建的可逆和自反转的多值加扰功能。 还提出了可能的多值逆变器的产生。 还公开了相应的多值解扰功能。 多值函数用于加扰和解扰多值信号的电路中。 多值函数也可用于信号发生器。 这样的信号发生器不需要使用乘法器。 还提出了由信号发生器产生的信号的自相关。 还描述了实现多值功能的电子电路。

公开(公告)号：US20070239812A1

公开(公告)日：2007-10-11

申请号：US11696261

申请日：2007-04-04

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F7/58

CPC classification number: G06F7/582

Abstract: N-valued scramblers, descramblers, sequence generators and sequence detectors with Linear Feedback Shift Registers (LFSRs) in Galois configuration are disclosed. Methods for creating detectors and descramblers in Fibonacci configuration corresponding to generators and scramblers with LFSRs in Galois configuration are also disclosed. Methods to calculate the content of a shift register in a sequence detector in Galois configuration are provided. N-valued scramblers and corresponding descramblers with LFSR in Galois configuration are disclosed. Binary and n-valued scramblers in Galois configuration and corresponding self-synchronizing descramblers with Linear Forward Connected Shift Registers are also disclosed. Systems applying scramblers and descramblers, or sequence generators and sequence detectors in Galois configuration are also provided.

Abstract translation: 公开了在Galois配置中使用线性反馈移位寄存器（LFSR）的N值扰频器，解扰器，序列发生器和序列检测器。 还公开了用于在Galois配置中对应于具有LFSR的发生器和扰频器的斐波纳契配置中创建检测器和解扰器的方法。 提供了在Galois配置中计算序列检测器中的移位寄存器的内容的方法。 披露了在Galois配置中使用L值的N值扰频器和相应的解扰器。 还公开了Galois配置中的二进制和n值加扰器以及具有线性前向连接移位寄存器的对应的自同步解扰器。 还提供了在Galois配置中应用加扰器和解扰器或序列发生器和序列检测器的系统。

公开(公告)号：US20070110229A1

公开(公告)日：2007-05-17

申请号：US11618986

申请日：2007-01-02

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04L9/28

CPC classification number: H03K19/20

Abstract: Reversible and self reversing multi-value scrambling functions created by applying multi-value inverters are disclosed. The generation of possible multi-value inverters is also presented. Corresponding multi-value descrambling functions are also disclosed. The multi-value functions are used in circuits that scramble and descramble multi-value signals. The multi-value functions can also be used in signal generators. Such signal generators do not require the use of multipliers. The auto-correlation of the signals generated by the signal generators is also presented. Electronic circuits that implement the multi-value functions are also described.

Abstract translation: 公开了通过应用多值逆变器创建的可逆和自反转的多值加扰功能。 还提出了可能的多值逆变器的产生。 还公开了相应的多值解扰功能。 多值函数用于加扰和解扰多值信号的电路中。 多值函数也可用于信号发生器。 这样的信号发生器不需要使用乘法器。 还提出了由信号发生器产生的信号的自相关。 还描述了实现多值功能的电子电路。

公开(公告)号：US20070088997A1

公开(公告)日：2007-04-19

申请号：US11534837

申请日：2006-09-25

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G01R31/28

CPC classification number: G06F7/584 ,  G06F2207/583 ,  G11C19/00

Abstract: Methods and apparatus to implement LFSRs and LFSR based sequence generators, detectors, scramblers and descramblers by addressable memory are disclosed. The methods and apparatus may be processing binary or n-valued symbols, with n>2. Methods to uniquely characterize n-valued Gold sequence are also disclosed. Self-synchronizing methods to detect sequences which can be decomposed into unique words are also disclosed. Methods and apparatus to implement Fibonacci and Galois LFSRs are disclosed.

Abstract translation: 公开了通过可寻址存储器来实现基于LFSR和LFSR的序列发生器，检测器，扰频器和解扰器的方法和装置。 方法和装置可以处理二进制或n值符号，其中n> 2。 还公开了唯一表征n值Gold序列的方法。 还公开了用于检测可分解为独特词的序列的自同步方法。 公开了实施斐波那契和伽罗瓦LFSR的方法和装置。

公开(公告)号：US20070071068A1

公开(公告)日：2007-03-29

申请号：US11534777

申请日：2006-09-25

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H04B1/713

CPC classification number: H04B1/7143

Abstract: Methods for transposing elements of a sequence according to a rule, wherein the rule is derived from pseudo-noise or pseudo-noise like binary and non-binary sequences are disclosed. Sequences of transposed symbols can be recovered by applying a reversing rule. Sets of orthogonal hopping and transposition rules are created by applying transposition rules upon themselves. Sets of orthogonal hopping and transposition rules are also created from binary and non-binary Gold sequences.

Abstract translation: 公开了根据规则来转移序列元素的方法，其中规则是从伪噪声或伪噪声得到的，如二进制和非二进制序列。 可以通过应用反转规则来恢复转置符号的序列。 通过对其自身应用换位规则创建正交跳跃和转置规则的集合。 正交跳变和转置规则的集合也是从二进制和非二进制Gold序列创建的。

公开(公告)号：US20070005673A1

公开(公告)日：2007-01-04

申请号：US11427498

申请日：2006-06-29

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: G06F7/58

CPC classification number: G06F7/58

Abstract: The invention discloses methods to create binary and non-binary sequences of a pseudo-random nature such that possible symbols occur at or almost at the same rate. The invention also discloses methods using symbol words of fixed lengths to generate unique sequences. These methods do not apply Linear Feedback Shift Registers (LFSRs). Methods to detect the presence of a pre-defined sequence are also disclosed. These methods do not apply LFSRs.

Abstract translation: 本发明公开了创建伪随机性质的二进制和非二进制序列的方法，使得可能的符号以或几乎相同的速率出现。 本发明还公开了使用固定长度的符号词来生成唯一序列的方法。 这些方法不适用线性反馈移位寄存器（LFSR）。 还公开了检测预定义序列的存在的方法。 这些方法不适用于LFSR。

公开(公告)号：US20060187092A1

公开(公告)日：2006-08-24

申请号：US11407496

申请日：2006-04-20

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M7/00

CPC classification number: H04B1/707 ,  H04J13/16

Abstract: Methods and apparatus for coding binary and multi-value sequences into higher value sequences are disclosed. Correlation methods for comparing lower-value sequences by first coding to higher value sequences and then calculating a correlation number are also disclosed. Methods and apparatus for resetting the coding rule during multi-value coding are also disclosed.

Abstract translation: 公开了将二进制和多值序列编码成较高值序列的方法和装置。 还公开了通过第一编码将较低值序列与较高值序列进行比较，然后计算相关数的相关方法。 还公开了在多值编码期间重置编码规则的方法和装置。

公开(公告)号：US07064684B2

公开(公告)日：2006-06-20

申请号：US11141336

申请日：2005-05-31

Applicant: Peter Lablans

Inventor： Peter Lablans

IPC: H03M5/16

CPC classification number: H04B1/707 ,  H04J13/16

Abstract: Methods and apparatus for coding binary and multi-value sequences into higher value sequences are disclosed. Correlation methods for comparing lower-value sequences by first coding to higher value sequences and then calculating a correlation number are also disclosed. Methods and apparatus for resetting the coding rule during multi-value coding are also disclosed.