公开(公告)号：US20160071232A1

公开(公告)日：2016-03-10

申请号：US14482828

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Adam T. Moerschell ,  James S. Blomgren

IPC: G06T1/60 ,  G06T1/20 ,  G06T7/00 ,  G06T7/40 ,  G06T11/00

CPC classification number: G06T1/60 ,  G06T15/04

Abstract: Techniques are disclosed relating to a cache configured to store state information for texture mapping. In one embodiment, a texture state cache includes a plurality of entries configured to store state information relating to one or more stored textures. In this embodiment, the texture state cache also includes texture processing circuitry configured to retrieve state information for one of the stored textures from one of the entries in the texture state cache and determine pixel attributes based on the texture and the retrieved state information. The state information may include texture state information and sampler state information, in some embodiments. The texture state cache may allow for reduced rending times and power consumption, in some embodiments.

Abstract translation: 公开了与被配置为存储用于纹理映射的状态信息的高速缓存相关的技术。 在一个实施例中，纹理状态高速缓存包括被配置为存储与一个或多个存储纹理相关的状态信息的多个条目。 在该实施例中，纹理状态高速缓存还包括纹理处理电路，其被配置为从纹理状态高速缓存中的一个条目中检索存储的纹理之一的状态信息，并且基于纹理和检索到的状态信息来确定像素属性。 在一些实施例中，状态信息可以包括纹理状态信息和采样器状态信息。 在一些实施例中，纹理状态高速缓存可以允许减少渲染时间和功耗。

公开(公告)号：US20250094357A1

公开(公告)日：2025-03-20

申请号：US18962158

申请日：2024-11-27

Applicant: Apple Inc.

Inventor： Jonathan M. Redshaw ,  Winnie W. Yeung ,  Benjiman L. Goodman ,  David K. Li ,  Zelin Zhang ,  Yoong Chert Foo

IPC: G06F12/126 ,  G06F12/0811 ,  G06F12/0891

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

公开(公告)号：US12190151B2

公开(公告)日：2025-01-07

申请号：US18054376

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Anjana Rajendran ,  Sheenam Jayaswal ,  Terence M. Potter ,  Yoong Chert Foo

IPC: G06F9/48

Abstract: Techniques are disclosed relating to multi-stage thread scheduling. In some embodiments, processor circuitry includes multiple channel pipelines for multiple channels and multiple execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may arbitrate among threads to assign threads to channels. Second scheduler circuitry may arbitrate among channels to assign an operation from a given channel to a given execution pipeline. The execution pipelines may provide backpressure information to the first scheduler circuitry based on execution status and the first scheduler circuitry may adjust priority of a thread for assignment to a channel based on the backpressure information. Disclosed techniques may reduce channel conflicts and starvation for execution resources.

公开(公告)号：US20240095035A1

公开(公告)日：2024-03-21

申请号：US18054401

申请日：2022-11-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Dzung Q. Vu ,  Robert Kenney

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3867 ,  G06F9/3887

Abstract: Techniques are disclosed relating to channel stalls or deactivations based on the latency of prior operations. In some embodiments, a processor includes a plurality of channel pipelines for a plurality of channels and a plurality of execution pipelines shared by the channel pipelines and configured to perform different types of operations provided by the channel pipelines. First scheduler circuitry may assign threads to channels and second scheduler circuitry may assign an operation from a given channel to a given execution pipeline based on decode of an operation for that channel. Dependency circuitry may, for a first operation that depends on a prior operation that uses one of the execution pipelines, determine, based on status information for the prior operation from the one of the execution pipelines, whether to stall the first operation or to deactivate a thread that includes the first operation from its assigned channel.

公开(公告)号：US11204774B1

公开(公告)日：2021-12-21

申请号：US17008518

申请日：2020-08-31

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Anjana Rajendran ,  Jeffrey A. Lohman ,  Terence M. Potter

IPC: G06F9/38

Abstract: Techniques are disclosed relating to a thread-group-scoped gate instruction. In some embodiments, graphics processor circuitry is configured to execute, for multiple SIMD groups of a thread group, a graphics program that includes a gate instruction. During execution of the gate instruction for a first SIMD group, the processor accesses state information to determine that a threshold number of other SIMD groups in the thread group have not yet executed the gate instruction. Based on the determination, the processor executes a particular set of instructions of the graphics program for the first SIMD group (that is not executed by one or more other SIMD groups that reach the gate instruction after the first SIMD group). For example, the particular set of instructions may be a utility program that performs one or more operations for the entire thread group but is only executed by a subset of the SIMD groups.

公开(公告)号：US10769746B2

公开(公告)日：2020-09-08

申请号：US14496934

申请日：2014-09-25

Applicant: Apple Inc.

Inventor： Liang Xia ,  Robert D. Kenney ,  Benjiman L. Goodman ,  Terence M. Potter

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/00

Abstract: A data queuing and format apparatus is disclosed. A first selection circuit may be configured to selectively couple a first subset of data to a first plurality of data lines dependent upon control information, and a second selection circuit may be configured to selectively couple a second subset of data to a second plurality of data lines dependent upon the control information. A storage array may include multiple storage units, and each storage unit may be configured to receive data from one or more data lines of either the first or second plurality of data lines dependent upon the control information.

公开(公告)号：US09519944B2

公开(公告)日：2016-12-13

申请号：US14475119

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Robert D. Kenney ,  Gregory D. Roberts

IPC: G06T1/20 ,  G06F9/30

CPC classification number: G06T1/20 ,  G06F9/30 ,  G06F9/3838 ,  G06F9/3877

Abstract: Techniques are disclosed relating to dependency resolution among processor pipelines. In one embodiment, an apparatus includes a first special-purpose pipeline configured to execute, in parallel, a first type of graphics instruction for a group of graphics elements and a second special-purpose pipeline configured to execute, in parallel, a second type of graphics instruction for the group of graphics elements. In this embodiment, the apparatus is configured, in response to dispatch of an instruction of the second type, to mark a particular instruction of the first type with information indicative of the dispatched instruction. In this embodiment, the particular instruction and the dispatched instruction correspond to the same group of graphics elements. In this embodiment, the apparatus is configured to stall performance of the dispatched instruction until the first special-purpose pipeline has completed execution of the marked particular instruction. Exemplary instruction types include interpolate and sample instructions.

Abstract translation: 公开了与处理器管线之间的依赖关系分辨有关的技术。 在一个实施例中，一种装置包括第一专用流水线，其被配置为并行地执行用于一组图形元件的第一类型的图形指令和被配置为并行地执行第二类型的图形元素的第二专用流水线 用于图形元素组的图形指令。 在该实施例中，该装置被配置为响应于第二类型的指令的分派，用指示发送指令的信息来标记第一类型的特定指令。 在本实施例中，特定指令和分派指令对应于同一组图形元素。 在本实施例中，该装置被配置为停止分派指令的性能，直到第一专用流水线已经完成了标记的特定指令的执行。 示例性指令类型包括内插和样本指令。

公开(公告)号：US20160063662A1

公开(公告)日：2016-03-03

申请号：US14475119

申请日：2014-09-02

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Robert D. Kenney ,  Gregory D. Roberts

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/30 ,  G06F9/3838 ,  G06F9/3877

Abstract: Techniques are disclosed relating to dependency resolution among processor pipelines. In one embodiment, an apparatus includes a first special-purpose pipeline configured to execute, in parallel, a first type of graphics instruction for a group of graphics elements and a second special-purpose pipeline configured to execute, in parallel, a second type of graphics instruction for the group of graphics elements. In this embodiment, the apparatus is configured, in response to dispatch of an instruction of the second type, to mark a particular instruction of the first type with information indicative of the dispatched instruction. In this embodiment, the particular instruction and the dispatched instruction correspond to the same group of graphics elements. In this embodiment, the apparatus is configured to stall performance of the dispatched instruction until the first special-purpose pipeline has completed execution of the marked particular instruction. Exemplary instruction types include interpolate and sample instructions.

Abstract translation: 公开了与处理器管线之间的依赖关系分辨有关的技术。 在一个实施例中，一种装置包括第一专用流水线，其被配置为并行地执行用于一组图形元件的第一类型的图形指令和被配置为并行地执行第二类型的图形元素的第二专用流水线 用于图形元素组的图形指令。 在该实施例中，该装置被配置为响应于第二类型的指令的分派，用指示发送指令的信息来标记第一类型的特定指令。 在本实施例中，特定指令和分派指令对应于同一组图形元素。 在本实施例中，该装置被配置为停止分派指令的性能，直到第一专用流水线已经完成了标记的特定指令的执行。 示例性指令类型包括内插和样本指令。

公开(公告)号：US20160055610A1

公开(公告)日：2016-02-25

申请号：US14574041

申请日：2014-12-17

Applicant: Apple Inc.

Inventor： Robert D. Kenney ,  Benjiman L. Goodman ,  Terence M. Potter

IPC: G06T1/20 ,  G09G5/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G09G5/001 ,  G09G5/363

Abstract: Techniques are disclosed relating to scheduling tasks for graphics processing. In one embodiment, a graphics unit is configured to render a frame of graphics data using a plurality of pass groups and the frame of graphics data includes a plurality of frame portions. In this embodiment, the graphics unit includes scheduling circuitry configured to receive a plurality of tasks, maintain pass group information for each of the plurality of tasks, and maintain relative age information for the plurality of frame portions. In this embodiment, the scheduling circuitry is configured to select a task for execution based on the pass group information and the age information. In some embodiments, the scheduling circuitry is configured to select tasks from an oldest frame portion and current pass group before selecting other tasks. This scheduling approach may result in efficient execution of various different types of graphics workloads.

Abstract translation: 公开了关于用于图形处理的调度任务的技术。 在一个实施例中，图形单元被配置为使用多个通行组来渲染图形数据帧，并且图形数据帧包括多个帧部分。 在该实施例中，图形单元包括配置成接收多个任务的调度电路，维护多个任务中的每个任务的通行组信息，并维护多个帧部分的相对年龄信息。 在该实施例中，调度电路被配置为基于通过组信息和年龄信息来选择用于执行的任务。 在一些实施例中，调度电路被配置为在选择其他任务之前从最旧的帧部分和当前的传递组中选择任务。 这种调度方法可以导致各种不同类型的图形工作负载的有效执行。