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公开(公告)号：US10609814B2
公开(公告)日：2020-03-31
申请号：US16414078
申请日：2019-05-16
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury
Abstract: A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
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公开(公告)号：US10352996B2
公开(公告)日：2019-07-16
申请号：US15350902
申请日：2016-11-14
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Timothy Thinh Mai
IPC: G06F11/20 , G01R31/317 , G01R31/319 , G06F11/00 , G01R31/3181 , G01R31/3177
Abstract: A backplane testing system includes a test backplane coupled to a test device chassis and including a first connector system, a second connector system, and channels that connect the first connector system and the second connector system. A first test device in a first test device slot on the test device chassis engages the first connector system and provides a loop back circuit for the first connector system. A second test device in a second test device slot on the test device chassis engages the second connector system. The second test device sends a test signal through a channel on the test backplane such that the test signal is provided to the loop back circuit on the first test device and received back through the channel. The second test device analyzes the test signal that is received to determine a testing compliance of the channel on the test backplane.
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公开(公告)号：US10299370B1
公开(公告)日：2019-05-21
申请号：US15927668
申请日：2018-03-21
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury
Abstract: A differential trace pair system includes a first conductive layer that is located immediately adjacent a first insulating layer. The system includes a second conductive layer that is located immediately adjacent the first insulating layer and opposite the first insulating layer from the first conductive layer, and includes an aperture that extends through the second conductive layer. A second insulating layer is located immediately adjacent the second conductive layer and opposite the second conductive layer from the first insulating layer. The system includes a first differential trace pair that is included in the second insulating layer and that includes a first differential trace that is positioned adjacent the aperture and references the second conductive layer, and a second differential trace that is longer than the first differential trace and that includes a first portion that is positioned adjacent the second conductive layer aperture and references the first conductive layer.
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公开(公告)号：US11924962B2
公开(公告)日：2024-03-05
申请号：US17451710
申请日：2021-10-21
Applicant: Dell Products L.P.
Inventor： Umesh Chandra
CPC classification number: H05K1/0206 , H05K1/0218 , H05K1/0298 , H05K1/116
Abstract: A printed circuit board (PCB), including: a processing unit; a plurality of layers; and a plurality of vias, each via extending through two or more of the layers, wherein a first via of the plurality of vias has a first pad at a first layer of the plurality of layers and a second via of the plurality of vias has a second pad at the first layer of the plurality of layers, wherein the first pad is conjoined with the second pad to form a first heatsink at the first layer that dissipates heat away from the processing unit.
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公开(公告)号：US11477890B2
公开(公告)日：2022-10-18
申请号：US16882427
申请日：2020-05-22
Applicant: DELL PRODUCTS L.P.
Inventor： Umesh Chandra , Bhyrav Mutnury
Abstract: A high-speed transmission circuit comprises a connector pin that serves as part of a signal path, has a first conductivity, and has a connector pin leg that is coupled to a pad that has a second conductivity lower than the first conductivity. The connector pin leg and at least a portion of the pad form a resonant sub-circuit coupled to the signal path. The second conductivity causes a reduction in insertion loss in the signal path by damping a current in the resonant sub-circuit.
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Patent Agency Ranking
公开(公告)号：US20220240366A1
公开(公告)日：2022-07-28
申请号：US17158524
申请日：2021-01-26
Applicant: Dell Products L.P.
Inventor： Umesh Chandra
IPC: H05K1/02
Abstract: A zoned dielectric loss circuit board system includes a board. A first differential trace is included in the board. A dielectric layer is included the board and that includes a first dielectric layer zone that engages the first differential trace and that includes first dielectric loss characteristics, and a second dielectric layer zone that is located immediately adjacent the first dielectric layer zone and that includes second dielectric loss characteristics that are greater than the first dielectric loss characteristics. A second differential trace may be included in the board in engagement with the second dielectric layer zone, and may have a second trace length that is shorter than a first trace length of the first differential trace.
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公开(公告)号：US20200245451A1
公开(公告)日：2020-07-30
申请号：US16260595
申请日：2019-01-29
Applicant: DELL PRODUCTS L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury
Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).
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公开(公告)号：US10667393B2
公开(公告)日：2020-05-26
申请号：US15861877
申请日：2018-01-04
Applicant: DELL PRODUCTS, L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury , Mallikarjun Vasa
Abstract: A circuit board assembly of an information handling system has stepped diameter vias that carry communication signals through printed circuit board (PCB) substrates. Each stepped diameter via has a first barrel portion of a first diameter that is drilled through a first portion of the PCB substrates and that is at least lined with a conductive material to electrically conduct a selected one of: (i) a direct current and (ii) a communication signal from an outer layer to an internal layer of the more than one PCB substrate. Each stepped diameter via further includes a second barrel portion that extends from the first barrel portion deeper into the PCB substrates. The second barrel portion has a second diameter that is less than the first diameter and the smaller second diameter improves signal integrity (SI).
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公开(公告)号：US20190274213A1
公开(公告)日：2019-09-05
申请号：US15910773
申请日：2018-03-02
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Chun-Lin Liao , Bhyrav M. Mutnury
Abstract: A circuit board pad mounting orientation system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. At least one connector pad receives the signal transmission line adjacent a first end of that connector pad. At least one connector pad includes a second end that provides a reduction in a width of that connector pad to indicate a mounting orientation for coupling to the connector pad that receives the signal transmission line. In a specific example, a first connector pad receives the signal transmission line, includes the first end, and includes the second end that is opposite the first connector pad from the first end and that provides the reduction in the width of the first connector pad to indicate the mounting orientation for coupling to the first connector pad.
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公开(公告)号：US10396760B1
公开(公告)日：2019-08-27
申请号：US16052879
申请日：2018-08-02
Applicant: Dell Products L.P.
Inventor： Umesh Chandra , Bhyrav M. Mutnury , Hamza S. Rahman
IPC: H05K1/02 , H03H11/28 , H01R13/6473
Abstract: A differential pair contact resistance asymmetry compensation system includes a board with a differential trace pair. A receiver device is coupled to the differential trace pair via a receiver device connector interface, and a transmitter device is coupled to the differential trace pair via a transmitter device connector interface. The transmitter device transmits a contact resistance compensation data stream to the receiver device via the differential trace pair. The transmitter device then adjusts an impedance provided by the transmitter device to compensate for a contact resistance asymmetry in the transmitter device connector interface. When the transmitter device determines that differential trace pair signal transmission capabilities for the differential trace pair in transmitting the contact resistance compensation data stream have improved in response to the adjustment of the impedance provided by the transmitter device, it sets the impedance provided by the transmitter device.
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