公开(公告)号：US08278994B2

公开(公告)日：2012-10-02

申请号：US13398116

申请日：2012-02-16

Applicant: David Kung ,  Leif Lund

Inventor： David Kung ,  Leif Lund

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

Abstract translation: 独立于温度的参考电路包括具有共同耦合的基极的第一和第二双极晶体管。 第一和第二电阻串联耦合在第二双极晶体管的发射极和地之间。 第一和第二电阻器分别具有第一和第二电阻值R1和R2，以及第三和第二温度系数TC3和TC2。 电阻值使得第一和第二双极晶体管的基极 - 发射极之间的电压TC1的温度系数基本上等于TC2×（R2 /（R1 + R2））+ TC3×（R1 /（ R1 + R2）），导致流经第一和第二双极晶体管中的每一个的参考电流在温度上基本恒定。 耦合在第二双极晶体管的节点和集电极之间的第三电阻器具有使得在节点处产生的参考电压在温度上基本恒定的值。

公开(公告)号：US20120068680A1

公开(公告)日：2012-03-22

申请号：US13272950

申请日：2011-10-13

Applicant: David Kung ,  Leif Lund

Inventor： David Kung ,  Leif Lund

IPC: G05F1/10

CPC classification number: H02M1/36 ,  H02M2001/0029

Abstract: An example circuit includes a regulator circuit coupled to first and second nodes. A capacitance circuit and a slew rate control circuit are coupled between the first and second nodes. The regulator circuit is coupled to charge a capacitance of the capacitance circuit with a charge current. The slew rate control circuit is coupled to control a change in voltage over change in time between the first and second nodes during a power up mode of the circuit. The slew rate control circuit further includes a switch and a resistor. The slew rate control circuit is coupled to switch the switch in response to a voltage between the first and second nodes. A voltage drop across the resistor is limited to a base-emitter voltage drop of a transistor coupled between the first and second nodes to set the change in voltage over change in time.

Abstract translation: 示例电路包括耦合到第一和第二节点的调节器电路。 电容电路和转换速率控制电路耦合在第一和第二节点之间。 该调节器电路被耦合以用充电电流对电容电路的电容进行充电。 耦合转换速率控制电路以在电路的上电模式期间控制电压在第一和第二节点之间的时间上的变化。 转换速率控制电路还包括开关和电阻器。 转换速率控制电路被耦合以响应于第一和第二节点之间的电压来切换开关。 电阻器两端的电压降限制在耦合在第一和第二节点之间的晶体管的基极 - 发射极电压降，以设置电压随时间的变化。

公开(公告)号：US08115457B2

公开(公告)日：2012-02-14

申请号：US12533977

申请日：2009-07-31

Applicant: Balu Balakrishnan ,  David Kung ,  Raymond Kenneth Orr ,  David Michael Hugh Matthews

Inventor： Balu Balakrishnan ,  David Kung ,  Raymond Kenneth Orr ,  David Michael Hugh Matthews

IPC: H02J7/00

CPC classification number: H02M1/32 ,  H02M1/12 ,  H02M1/126 ,  H02M1/36 ,  H02M2001/322

Abstract: A circuit to discharge a capacitance between input terminals of a power system is disclosed. An example circuit includes a control circuit coupled to an input of a power system. The control circuit is coupled to detect whether an electrical energy source is coupled to an input of the power system. A switch is also included and is coupled to the control circuit and to the input of the power system. The control circuit is coupled to drive the switch in a first operating mode when the electrical energy source is coupled to the input of the power system. The control circuit is coupled to drive the switch in a second operating mode when the electrical energy source is uncoupled from the input of the power system. A capacitance coupled between input terminals of the input of the power system is discharged through the switch to a threshold voltage in less than a maximum period of time from when the electrical power source is uncoupled from the input terminals of the power system.

Abstract translation: 公开了一种用于在电力系统的输入端子之间放电的电路。 示例电路包括耦合到电力系统的输入的控制电路。 控制电路被耦合以检测电能源是否耦合到电力系统的输入端。 还包括开关并且耦合到控制电路和电力系统的输入。 当电能源耦合到电力系统的输入端时，控制电路被耦合以在第一操作模式下驱动开关。 当电能源与电力系统的输入分离时，控制电路被耦合以在第二操作模式下驱动开关。 耦合在电力系统的输入端的输入端之间的电容通过开关从小于电力从电力系统的输入端分离的最大时间段内被释放到阈值电压。

公开(公告)号：US20110298529A1

公开(公告)日：2011-12-08

申请号：US13136921

申请日：2011-08-15

Applicant: David Kung ,  Leif Lund

Inventor： David Kung ,  Leif Lund

IPC: H03K17/78

CPC classification number: G05F3/30

Abstract: A temperature independent reference circuit includes first and second bipolar transistors with commonly coupled bases. First and second resistors are coupled in series between the emitter of the second bipolar transistor and ground. The first and second resistors have first and second resistance values, R1 and R2, and third and second temperature coefficients, TC3 and TC2, respectively. The resistance values being such that a temperature coefficient of a difference between the base-emitter voltages of the first and second bipolar transistors, TC1, is substantially equal to TC2×(R2/(R1+R2))+TC3×(R1/(R1+R2)), resulting in a reference current flowing through each of the first and second bipolar transistors that is substantially constant over temperature. A third resistor coupled between a node and the collector of the second bipolar transistor has a value such that a reference voltage generated at the node is substantially constant over temperature.

公开(公告)号：US20110080761A1

公开(公告)日：2011-04-07

申请号：US12587398

申请日：2009-10-06

Applicant: David Kung

Inventor： David Kung

IPC: H02M7/217

CPC classification number: H02M7/219 ,  H02M7/217 ,  H02M7/2176 ,  H02M2007/2195

Abstract: An integrated circuit (IC) comprises a rectifier/regulator circuit coupled to receive an ac source voltage and output a regulated dc voltage. The rectifier/regulator circuit includes first and second switching elements that provide charging current when enabled. The first and second switching elements do not provide charging current when disabled. A sensor circuit is coupled to sense the regulated dc voltage and generate a feedback control signal coupled to the rectifier/regulator circuit that enables the first and second switching elements when the regulated dc voltage is above a target voltage, and disables the first and second switching elements when the regulated dc voltage is below the target voltage.

Abstract translation: 集成电路（IC）包括整流器/调节器电路，其耦合以接收交流电源电压并输出调节的直流电压。 整流器/调节器电路包括当使能时提供充电电流的第一和第二开关元件。 禁用时，第一和第二开关元件不提供充电电流。 传感器电路被耦合以感测调节的直流电压并且产生耦合到整流器/调节器电路的反馈控制信号，其在调节的直流电压高于目标电压时使能第一和第二开关元件，并且禁用第一和第二开关 当调节的直流电压低于目标电压时的元件。

公开(公告)号：US20100301821A1

公开(公告)日：2010-12-02

申请号：US12477058

申请日：2009-06-02

Applicant: David Kung ,  William M. Polivka

Inventor： David Kung ,  William M. Polivka

IPC: G05F1/10

CPC classification number: H02M3/33523 ,  H02M2001/0009

Abstract: An example controller includes a constant current control circuit and an integrator included in the constant current control circuit. The constant current control circuit is to be coupled to receive an input current sense signal, an input voltage sense signal, and an output voltage sense signal. The control circuit is adapted to regulate an output current of a power supply by generating a control signal to control switching of a switch. The integrator is coupled to integrate the input current sense signal during a switching period of the control signal to generate an integrated signal representative of a charge taken from an input voltage source of the power supply. The constant current control circuit is adapted to control the switching of the switch such that the integrated signal is proportional to a ratio of the output voltage sense signal to the input voltage sense signal.

Abstract translation: 示例性控制器包括恒流控制电路和包括在恒流控制电路中的积分器。 恒流控制电路将被耦合以接收输入电流感测信号，输入电压感测信号和输出电压感测信号。 控制电路适于通过产生控制信号来调节电源的输出电流来控制开关的切换。 耦合该积分器以在控制信号的开关周期期间集成输入电流感测信号，以产生代表从电源的输入电压源获取的电荷的积分信号。 恒流控制电路适于控制开关的开关，使得积分信号与输出电压感测信号与输入电压感测信号的比例成比例。

公开(公告)号：US20080172674A1

公开(公告)日：2008-07-17

申请号：US11952483

申请日：2007-12-07

Applicant: Monfor Yee ,  Wu Cao ,  Hui Xu ,  Anil Kumar Samudrala ,  Balaji Gadhiraju ,  Kurinchi Kumaran ,  David Kung

Inventor： Monfor Yee ,  Wu Cao ,  Hui Xu ,  Anil Kumar Samudrala ,  Balaji Gadhiraju ,  Kurinchi Kumaran ,  David Kung

IPC: G06F9/46

CPC classification number: G06F9/5038 ,  G06F17/30563 ,  G06F2209/5017

Abstract: A computer readable storage medium includes executable instructions to assess system cache resources, inter-process communication requirements and staging requirements to divide an extract, transform, load (ETL) dataflow task into a plurality of sub-tasks. The sub-tasks are then executed in parallel on distributed resources.

Abstract translation: 计算机可读存储介质包括用于评估系统高速缓存资源，进程间通信需求和分段要求的可执行指令，以将提取，变换，加载（ETL）数据流任务划分为多个子任务。 然后在分布式资源上并行执行子任务。

公开(公告)号：US20080042140A1

公开(公告)日：2008-02-21

申请号：US11847608

申请日：2007-08-30

Applicant: Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

Inventor： Syed Alam ,  Ibrahim Elfadel ,  Kathryn Guarini ,  Meikei Ieong ,  Prabhakar Kudva ,  David Kung ,  Mark Lavin ,  Arifur Rahman

IPC: H01L29/04

CPC classification number: H01L27/0688 ,  H01L21/2007 ,  H01L21/84 ,  H01L27/1203

Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract translation: 三维（3D）集成电路（IC），3D IC芯片和3D IC芯片的制造方法。 该芯片包括多层电路，例如硅绝缘体（SOI）CMOS IC层，每层包括电路元件。 这些层可以平行地形成，并且一层附着到另一层以形成层叠的3D芯片。

公开(公告)号：US20070028193A1

公开(公告)日：2007-02-01

申请号：US11460537

申请日：2006-07-27

Applicant: Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

Inventor： Anthony Correale ,  David Kung ,  Douglass Lamb ,  Zhigang Pan ,  Ruchir Puri ,  David Wallach

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068 ,  G06F2217/78 ,  H01L27/118

Abstract: An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (Vddl) supply and a high voltage island powered by a high voltage (Vddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Abstract translation: 一种用于降低IC设计功耗的集成电路（IC）设计，方法和程序产品。 IC以电路行组织。 电路行可以包括由低电压（Vdd）电源供电的低压岛和由高电压（Vdd）供电供电的高电压岛。 包括电池，锁存器和宏的电路元件放置有高电压或低电压岛，以尽量减少IC功率，同时保持整体性能。 电平转换器可以放置高压电路元件。

公开(公告)号：US20060190899A1

公开(公告)日：2006-08-24

申请号：US10905970

申请日：2005-01-28

Applicant: William Migatz ,  Paul Campbell ,  David Hathaway ,  David Kung ,  Ruchir Puri ,  Louise Trevillyan

Inventor： William Migatz ,  Paul Campbell ,  David Hathaway ,  David Kung ,  Ruchir Puri ,  Louise Trevillyan

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F1/10

Abstract: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

Abstract translation: 描述了一种方法，系统和程序产品，用于通过为集成电路中的一组时钟树叶元素中的每一个确定允许的布局区域来在集成电路上生成时钟分配网络。 通过确定和相交不同约束下的一组子区域来生成该允许的放置区域，每个子区域标识其中放置时钟树叶元素的区域以满足相应的约束。 确定子区域的约束包括松弛和拥挤约束形式的时间约束。 在确定了允许的放置区域之后，时钟树叶元素被聚集，并且每个时钟树叶元素被放置在其允许的放置区域内的位置，这使得该聚类的一些成本函数最小化。