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    Structure and method to improve ETSOI MOSFETS with back gate
    21.
    发明授权
    Structure and method to improve ETSOI MOSFETS with back gate 有权
    具有后栅的ETSOI MOSFET的结构和方法

    公开(公告)号：US09337259B2

    公开(公告)日：2016-05-10

    申请号：US14154438

    申请日：2014-01-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Pranita Kerber ,  Ali Khakifirooz ,  Balasubramanian Pranatharthiharan

    IPC: H01L29/06 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66

    CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

    Abstract: A structure to improve ETSOI MOSFET devices includes a wafer having regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in the hole.

    Abstract translation: 改进ETSOI MOSFET器件的结构包括具有至少覆盖在第二半导体层上的氧化物层上的第一半导体层的区域的晶片。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 栅极结构形成在第一半导体层之上，并且在涉及的湿清洗期间，STI纹理腐蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔没有完全着陆，至少部分地延伸到STI中，并且绝缘材料沉积在孔中。

    Bi-layer gate cap for self-aligned contact formation
    22.
    发明授权
    Bi-layer gate cap for self-aligned contact formation 有权
    用于自对准接触形成的双层栅极盖

    公开(公告)号：US09064801B1

    公开(公告)日：2015-06-23

    申请号：US14161721

    申请日：2014-01-23

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc. ,  Samsung Electronics Co., Ltd.

    Inventor： David V. Horak ,  Jin Wook Lee ,  Daniel Pham ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan

    IPC: H01L21/336 ,  H01L21/28 ,  H01L29/51 ,  H01L21/283

    CPC classification number: H01L21/283 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    Abstract: A method of forming a semiconductor structure includes forming a metal gate above a semiconductor substrate and gate spacers adjacent to the metal gate surrounded by an interlevel dielectric (ILD) layer. The gate spacers and the metal gate are recessed until a height of the metal gate is less than a height of the gate spacers. An etch stop liner is deposited above the gate spacers and the metal gate. A gate cap is deposited above the etch stop liner to form a bi-layer gate cap. A contact hole is formed in the ILD layer adjacent to the metal gate, the etch stop liner in the bi-layer gate cap prevents damage of the gate spacers during formation of the contact hole. A conductive material is deposited in the contact hole to form a contact to a source-drain region in the semiconductor substrate.

    Abstract translation: 形成半导体结构的方法包括在半导体衬底之上形成金属栅极和邻近由层间电介质（ILD）层围绕的金属栅极的栅极间隔。 栅极间隔物和金属栅极凹入直到金属栅极的高度小于栅极间隔物的高度。 蚀刻停止衬垫沉积在栅极间隔物和金属栅极上方。 栅极盖沉积在蚀刻停止衬垫上方以形成双层栅极盖。 在与金属栅极相邻的ILD层中形成接触孔，双层栅极帽中的蚀刻停止衬垫防止在形成接触孔期间损坏栅极间隔物。 导电材料沉积在接触孔中以与半导体衬底中的源极 - 漏极区形成接触。

    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE
    23.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE WITH A PROTECTED GATE CAP LAYER AND THE RESULTING DEVICE 有权
    形成具有保护盖板层和结构设备的半导体器件的方法

    公开(公告)号：US20150041869A1

    公开(公告)日：2015-02-12

    申请号：US14526126

    申请日：2014-10-28

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

    IPC: H01L29/423 ,  H01L29/51

    CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

    Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

    Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

    Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
    24.
    发明授权
    Methods of forming a semiconductor device with a protected gate cap layer and the resulting device 有权
    用保护的栅极盖层形成半导体器件的方法和所得到的器件

    公开(公告)号：US08906754B2

    公开(公告)日：2014-12-09

    申请号：US13839802

    申请日：2013-03-15

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

    IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/42364 ,  H01L21/28247 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

    Abstract: One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.

    Abstract translation: 本文公开的一种方法包括形成封装并保护栅极盖层的第一和第二栅极盖保护层。 本文公开的新型晶体管器件包括位于半导体衬底上方的栅极结构，邻近栅极结构定位的间隔结构，位于衬底上方并围绕间隔结构的绝缘材料层，位于栅极结构之上的栅极盖层， 所述间隔结构以及封装所述栅极盖层的栅极帽保护材料，其中所述栅极盖保护材料的部分位于所述栅极盖层和所述栅极结构之间，所述间隔物结构和所述绝缘材料层。

    Dual liner silicide
    25.
    发明授权
    Dual liner silicide 有权

    公开(公告)号：US10395995B2

    公开(公告)日：2019-08-27

    申请号：US15956082

    申请日：2018-04-18

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

    Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

    Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

    Devices and methods of cobalt fill metallization
    28.
    发明授权
    Devices and methods of cobalt fill metallization 有权

    公开(公告)号：US10128151B2

    公开(公告)日：2018-11-13

    申请号：US15381826

    申请日：2016-12-16

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal Kamineni ,  James Kelly ,  Praneet Adusumilli ,  Oscar Van Der Straten ,  Balasubramanian Pranatharthiharan

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

    Abstract: Devices and methods of fabricating integrated circuit devices via cobalt fill metallization are provided. A method includes, for instance, providing an intermediate semiconductor device having at least one trench, forming at least one layer of semiconductor material on the device, depositing a first cobalt (Co) layer on the second layer, and performing an anneal reflow process on the device. Also provided are intermediate semiconductor devices. An intermediate semiconductor device includes, for instance, at least one trench formed within the device, the trench having a bottom portion and sidewalls, at least one layer of semiconductor material disposed on the device, a first cobalt (Co) layer disposed on the at least one layer of semiconductor material, wherein the at least one layer of semiconductor material includes at least a first semiconductor material and a second semiconductor material.

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