公开(公告)号：US20190148373A1

公开(公告)日：2019-05-16

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/0276 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US10290544B2

公开(公告)日：2019-05-14

申请号：US15728632

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Chanro Park

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L23/528

Abstract: One illustrative method disclosed herein may include forming a contact etching structure in a layer of insulating material positioned above first and second lower conductive structures, wherein at least a portion of the contact etching structure is positioned laterally between the first and second lower conductive structures, forming a first conductive line and a first conductive contact adjacent a first side of the contact etching structure and forming a second conductive line and a second conductive contact adjacent a second side of the contact etching structure, wherein a spacing between the first and second conductive lines is approximately equal to a dimension of the contact etching structure.

公开(公告)号：US10230000B2

公开(公告)日：2019-03-12

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

公开(公告)号：US20190074224A1

公开(公告)日：2019-03-07

申请号：US15695229

申请日：2017-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Min Gyu Sung ,  Edward Joseph Nowak ,  Nigel G. Cave ,  Lars Liebmann ,  Daniel Chanemougame ,  Andreas Knorr

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: The disclosure is directed to gate all-around integrated circuit structures, finFETs having a dielectric isolation, and methods of forming the same. The gate all-around integrated circuit structure may include a first insulator region within a substrate; a pair of remnant liner stubs disposed within the first insulator region; a second insulator region laterally adjacent to the first insulator region within the substrate; a pair of fins over the first insulator region, each fin in the pair of fins including an inner sidewall facing the inner sidewall of an adjacent fin in the pair of fins and an outer sidewall opposite the inner sidewall; and a gate structure substantially surrounding an axial portion of the pair of fins and at least partially disposed over the first and second insulator regions, wherein each remnant liner stub is substantially aligned with the inner sidewall of a respective fin of the pair of fins.

公开(公告)号：US20180315821A1

公开(公告)日：2018-11-01

申请号：US15581053

申请日：2017-04-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hao Tang ,  Cheng Chi ,  Daniel Chanemougame ,  Lars W. Liebmann ,  Mark V. Raymond

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45

Abstract: One illustrative method disclosed includes, among other things, forming a conductive source/drain metallization structure adjacent a gate, forming a gate contact opening that exposes at least a portion of a front face of the conductive source/drain metallization structure and a portion of an upper surface of a gate structure of the gate. In this example, the method further includes forming an internal insulating spacer within the gate contact opening that is positioned on and in contact with the exposed portion of the front face, wherein the spacer leaves at least a portion of the upper surface of the gate structure exposed, and forming a conductive gate contact structure (CB) in the conductive gate contact opening.

公开(公告)号：US10090193B1

公开(公告)日：2018-10-02

申请号：US15814445

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Lars Liebmann ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates stacked pair(s) of field effect transistors (FETs), where each stacked pair has a shared gate. The structure also includes an irregular-shaped buried interconnect that connects source/drain regions that are on opposite sides of the shared gate and at different levels (i.e., a lower FET's source/drain region on one side of the shared gate to an upper FET's source/drain region on the opposite side). Also disclosed is a method for forming the structure by forming, during different process stages, different sections of an irregular-shaped cavity (including sections that expose surfaces of the source/drain regions at issue and a section with sidewalls lined by a dielectric spacer) and filling the different sections with sacrificial material. When all of the sections are completed, the sacrificial material is selectively removed, thereby creating the irregular-shaped cavity. Then, the buried interconnect is formed within the cavity.

公开(公告)号：US10797138B2

公开(公告)日：2020-10-06

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10658243B2

公开(公告)日：2020-05-19

申请号：US16002385

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Chanro Park

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure relates to methods for forming replacement metal gate (RMG) structures and related structures. A method may include: forming a portion of sacrificial material around each fin of a set of adjacent fins; forming a first dielectric region between the portions of sacrificial material; forming a second dielectric region on the first dielectric region; forming an upper source/drain region from an upper portion of each fin; removing only the second dielectric region and the sacrificial material; and forming a work function metal (WFM) in place of the second dielectric region and the sacrificial material. The semiconductor structure may include gate structures surrounding adjacent fins; a first dielectric region between the gate structures; a second dielectric region above the first dielectric region and between the gate structures; and a liner between the first dielectric region and the gate structures such that the second dielectric region directly contacts the gate structures.

公开(公告)号：US10651284B2

公开(公告)日：2020-05-12

申请号：US15791650

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Youngtag Woo ,  Daniel Chanemougame ,  Bipul C. Paul ,  Lars W. Liebmann ,  Heimanu Niebojewski ,  Xuelian Zhu ,  Lei Sun ,  Hui Zang

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.