公开(公告)号：US10648096B2

公开(公告)日：2020-05-12

申请号：US14948463

申请日：2015-11-23

Applicant: Infineon Technologies AG

Inventor： Werner Robl ,  Michael Melzl ,  Manfred Schneegans ,  Bernhard Weidgans ,  Franziska Haering

IPC: C25D5/50 ,  C25D17/12 ,  C25D3/38 ,  C25D3/48 ,  C25D3/46 ,  C25D3/12 ,  C25D3/52 ,  C25D3/32 ,  C25D15/00 ,  C25D7/12 ,  H01L21/288 ,  H01L23/532

Abstract: An electrolyte may be provided. The electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C., and a water soluble metal salt, and the electrolyte may be free from carbon nanotubes. In various embodiments, a method of forming a metal layer may be provided: The method may include depositing a metal layer on a carrier using an electrolyte, wherein the electrolyte may include at least one additive configured to decompose or evaporate at a temperature above approximately 100° C. and a water soluble metal salt, wherein the electrolyte is free from carbon nanotubes; and annealing the metal layer to form a metal layer comprising a plurality of pores. In various embodiments, a semiconductor device may be provided. The semiconductor device may include a metal layer including a plurality of pores, wherein the plurality of pores may be formed in the metal layer as remnants of an additive having resided in the plurality of pores and having at least partially decomposed or evaporated. To keep a high elasticity over a wide temperature range (up to 450° C.), an adhesion layer may stabilize the metal grain boundaries and may fix dislocation gliding inside metal grains. In various embodiments, a metal layer is provided. The metal layer may include a plurality of pores having ellipsoidal or spheroidal shape.

公开(公告)号：US09911686B2

公开(公告)日：2018-03-06

申请号：US15155271

申请日：2016-05-16

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Andreas Meiser ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC: H01L23/528 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L21/4807 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0603 ,  H01L2224/08245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0532 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

公开(公告)号：US20160379947A1

公开(公告)日：2016-12-29

申请号：US15191777

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01074

Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.

Abstract translation: 半导体器件包括具有导电结构的半导体管芯。 金属结构电连接到导电结构并且包含第一金属。 辅助层堆叠夹在导电结构和金属结构之间，并包括含有第二金属的粘附层。 辅助层堆叠还包括在粘附层和导电结构之间的金属扩散阻挡层。 粘附层含有第一金属和第二金属。

公开(公告)号：US09449876B2

公开(公告)日：2016-09-20

申请号：US14158398

申请日：2014-01-17

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Schneegans

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/66 ,  H01L23/00 ,  B23H1/00 ,  B23H9/00

CPC classification number: H01L21/78 ,  B23H1/00 ,  B23H9/00 ,  H01L22/10 ,  H01L22/34 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.

Abstract translation: 分离半导体晶片的各个管芯的方法包括在半导体晶片的第一表面上形成金属层，所述半导体晶片包括多个管芯，将多个管芯彼此分离，并将金属层进行放电加工成 各个片段保持附着于一个模具。 还提供了通过这种方法制造的相应的半导体管芯。

公开(公告)号：US20160035654A1

公开(公告)日：2016-02-04

申请号：US14614119

申请日：2015-02-04

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Andreas Meiser

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L21/78 ,  H01L23/528

CPC classification number: H01L23/49562 ,  H01L21/4807 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/32 ,  H01L24/49 ,  H01L24/94 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/0603 ,  H01L2224/08245 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0532 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device regions are formed adjacent the first side. The method further includes forming a seed layer over the first side of the semiconductor substrate, and forming a patterned resist layer over the seed layer. A contact pad is formed over the seed layer within the patterned resist layer. The method further includes removing the patterned resist layer after forming the contact pad to expose a portion of the seed layer underlying the patterned resist layer, and forming a protective layer over the exposed portion of the seed layer.

公开(公告)号：US20160035560A1

公开(公告)日：2016-02-04

申请号：US14451043

申请日：2014-08-04

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Martin Mischitz ,  Michael Roesner ,  Michael Pinczolits

IPC: H01L21/02 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/49551 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/28 ,  H01L24/32 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03602 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

Abstract: In accordance with an alternative embodiment of the present invention, a method for forming a semiconductor device includes applying a paste over a semiconductor substrate, and forming a ceramic carrier by solidifying the paste. The semiconductor substrate is thinned using the ceramic carrier as a carrier.

Abstract translation: 根据本发明的替代实施例，一种用于形成半导体器件的方法包括在半导体衬底上施加糊料，并通过固化糊料形成陶瓷载体。 使用陶瓷载体作为载体来减薄半导体衬底。

公开(公告)号：US10340227B2

公开(公告)日：2019-07-02

申请号：US15071375

申请日：2016-03-16

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Manfred Schneegans

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  C22C19/03

Abstract: In various embodiments, a die is provided. The die may include a die body, and at least one of a front side metallization structure on a front side of the die body and a back side metallization structure on a back side of the die body such that the die is plane or includes a positive radius of curvature at a die attach process temperature range.

公开(公告)号：US10090265B2

公开(公告)日：2018-10-02

申请号：US15191777

申请日：2016-06-24

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC: H01L23/48 ,  H01L23/00 ,  H01L29/417 ,  H01L29/40 ,  H01L23/532 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor die that having a conductive structure. A metal structure is electrically connected to the conductive structure and contains a first metal. An auxiliary layer stack is sandwiched between the conductive structure and the metal structure and includes an adhesion layer that contains a second metal. The auxiliary layer stack further includes a metal diffusion barrier layer between the adhesion layer and the conductive structure. The adhesion layer contains the first metal and a second metal.

公开(公告)号：US20180145045A1

公开(公告)日：2018-05-24

申请号：US15817810

申请日：2017-11-20

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Rainer Pelzer ,  Manfred Schneegans

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/4502 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10157 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2224/45099

Abstract: A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

公开(公告)号：US09929111B2

公开(公告)日：2018-03-27

申请号：US15461500

申请日：2017-03-17

Applicant: Infineon Technologies AG

Inventor： Martin Mischitz ,  Markus Heinrici ,  Barbara Eichinger ,  Manfred Schneegans ,  Stefan Krivec

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02 ,  H01L23/532 ,  H01L21/762

CPC classification number: H01L24/03 ,  H01L21/02203 ,  H01L21/02513 ,  H01L21/76259 ,  H01L23/53238 ,  H01L24/05 ,  H01L2224/0331 ,  H01L2224/0345 ,  H01L2224/03505 ,  H01L2224/03602 ,  H01L2224/03616 ,  H01L2224/0384 ,  H01L2224/05541 ,  H01L2224/05551 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface; wherein a porosity of the first layer is greater than a porosity of the substrate and greater than a porosity of the second layer; wherein the second layer is formed by physical vapor deposition; and wherein the first layer and the second layer are formed from the same solid material.