公开(公告)号：US10135162B1

公开(公告)日：2018-11-20

申请号：US15842962

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Jose A. Hejase ,  Wiren D. Becker ,  Daniel Dreps ,  Sungjun Chun ,  Brian Beaman

IPC: H01R9/00 ,  H05K3/00 ,  H01R12/70 ,  H01R12/71 ,  H01R43/18 ,  H01R43/20 ,  H01R13/24

Abstract: Embodiments of the present invention include a method for fabricating a hybrid land grid array connector and the resulting structures. A body is provided. The body includes a first plurality of holes and a second plurality of holes. A conductive layer is deposited on the top and bottom surfaces of the body and the wall surfaces of the first plurality of holes resulting in the top and bottom surfaces being electrically common. The conductive layer is removed from the wall surfaces of a first subset of the first plurality of holes. A portion of the conductive layer is removed from the top surface of the body and the bottom surface of the body from an area surrounding the first subset of the first plurality of holes.

公开(公告)号：US20180075180A1

公开(公告)日：2018-03-15

申请号：US15813236

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

公开(公告)号：US20170316141A1

公开(公告)日：2017-11-02

申请号：US15430970

申请日：2017-02-13

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

公开(公告)号：US09485866B2

公开(公告)日：2016-11-01

申请号：US15010480

申请日：2016-01-29

Applicant: International Business Machines Corporation

Inventor： Mahesh Bohra ,  Sungjun Chun ,  Jesus Montanez ,  Daniel I. Rodriguez

IPC: H05K1/11 ,  H05K1/09 ,  H05K1/16 ,  H05K1/14 ,  H05K1/02 ,  H05K3/00 ,  H05K3/22 ,  H05K3/32 ,  H05K1/18

CPC classification number: H05K1/144 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/183 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/325 ,  H05K2201/09845 ,  H05K2203/0207 ,  Y10T29/49126 ,  Y10T156/1056

Abstract: A device has a base with a mounting surface with a length and a stack, the stack having a diameter smaller than the length and fastened to the mounting surface. The stack may have a plurality of stack conductive layers in addition to a plurality of insulating layers that separate each of the plurality of stack conductive layers. The stack conductive layers may be separated in a manner that aligns them with corresponding printed circuit board conductive layers when the stack portion of the device is inserted into an aperture in a printed circuit board.

Abstract translation: 装置具有具有长度和堆叠的安装表面的基座，该堆叠具有小于该长度的直径并且紧固到安装表面。 除了分离多个堆叠导电层中的每一个的多个绝缘层之外，堆叠可以具有多个堆叠导电层。 当将器件的堆叠部分插入到印刷电路板的孔中时，叠层导电层可以以将它们与相应的印刷电路板导电层对准的方式分离。

公开(公告)号：US20150282331A1

公开(公告)日：2015-10-01

申请号：US14732885

申请日：2015-06-08

Applicant: International Business Machines Corporation

Inventor： Mahesh Bohra ,  Sungjun Chun ,  Jesus Montanez ,  Daniel I. Rodriguez

IPC: H05K3/32 ,  H05K3/00

CPC classification number: H05K1/144 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/115 ,  H05K1/183 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/325 ,  H05K2201/09845 ,  H05K2203/0207 ,  Y10T29/49126 ,  Y10T156/1056

Abstract: A device has a base with a mounting surface with a length and a stack, the stack having a diameter smaller than the length and fastened to the mounting surface. The stack may have a plurality of stack conductive layers in addition to a plurality of insulating layers that separate each of the plurality of stack conductive layers. The stack conductive layers may be separated in a manner that aligns them with corresponding printed circuit board conductive layers when the stack portion of the device is inserted into an aperture in a printed circuit board.

Abstract translation: 装置具有具有长度和堆叠的安装表面的基座，该堆叠具有小于该长度的直径并且紧固到安装表面。 除了分离多个堆叠导电层中的每一个的多个绝缘层之外，堆叠可以具有多个堆叠导电层。 当将器件的堆叠部分插入到印刷电路板的孔中时，叠层导电层可以以将它们与相应的印刷电路板导电层对准的方式分离。

公开(公告)号：US20240213217A1

公开(公告)日：2024-06-27

申请号：US18086575

申请日：2022-12-21

Applicant: International Business Machines Corporation

Inventor： David Michael Audette ,  Grant Wagner ,  Steven Paul Ostrander ,  Hubert Harrer ,  Arvind Kumar ,  Thomas Anthony Wassick ,  Matthew Sean Grady ,  Sungjun Chun

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/1412 ,  H01L2224/16227

Abstract: An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.

公开(公告)号：US10657308B2

公开(公告)日：2020-05-19

申请号：US15800151

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50 ,  G06F30/394

Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

公开(公告)号：US20180068048A1

公开(公告)日：2018-03-08

申请号：US15813233

申请日：2017-11-15

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

公开(公告)号：US20180060478A1

公开(公告)日：2018-03-01

申请号：US15800151

申请日：2017-11-01

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

公开(公告)号：US09881115B2

公开(公告)日：2018-01-30

申请号：US15139653

申请日：2016-04-27

Applicant: International Business Machines Corporation

Inventor： Sungjun Chun ,  Matteo Cocchini ,  Michael A. Cracraft

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5081

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.