公开(公告)号：US20180204725A1

公开(公告)日：2018-07-19

申请号：US15919918

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Victorina Poenariu ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/861 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US09997515B2

公开(公告)日：2018-06-12

申请号：US15681607

申请日：2017-08-21

Applicant: Infineon Technologies AG

Inventor： Roland Rupp ,  Romain Esteve ,  Dethard Peters

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/16 ,  H01L29/10 ,  H01L29/04 ,  H01L29/40 ,  H01L29/861

CPC classification number: H01L27/0664 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/8613

Abstract: A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted to a crystal direction by an off-axis angle, wherein an absolute value of the off-axis angle is in a range from 2 degree to 12 degree. The trench gate structures extend oriented along the crystal direction. Portions of the semiconductor body between neighboring trench gate structures form transistor mesas. Sidewalls of the transistor mesas deviate from a normal to the mean surface plane by not more than 5 degree.

公开(公告)号：US20180158920A1

公开(公告)日：2018-06-07

申请号：US15866755

申请日：2018-01-10

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Dethard Peters ,  Romain Esteve ,  Wolfgang Bergner ,  Thomas Aichinger ,  Daniel Kueck ,  Roland Rupp ,  Bernd Zippelius ,  Karlheinz Feldrapp ,  Christian Strenger

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/739 ,  H01L29/10 ,  H01L29/20 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/4236 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7827

Abstract: A semiconductor device includes a semiconductor body formed from a semiconductor material with a band-gap of at least 2.0 eV, the semiconductor body having a diode region and a source region. The semiconductor device further includes a trench gate structure having a first sidewall and a second sidewall opposite the first sidewall, the first sidewall and the second sidewall extending along a common longitudinal direction. A doping concentration of a first doping type is higher in the diode region than in the source region. The trench gate structure projects from a first surface of the semiconductor body into the semiconductor body. A first portion of the second sidewall at the first surface is directly adjoined by the source region. A second portion of the second sidewall is in direct contact with the diode region. Additional semiconductor device embodiments are provided.

公开(公告)号：US09960230B2

公开(公告)日：2018-05-01

申请号：US15400299

申请日：2017-01-06

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.

公开(公告)号：US09876103B2

公开(公告)日：2018-01-23

申请号：US15291168

申请日：2016-10-12

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L21/04 ,  H01L29/423 ,  H01L29/04 ,  H01L29/10 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/7805 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

Abstract: A transistor cell includes a drift region, a source region, and a body region arranged between the source region and the drift region in a semiconductor body. A drain region is below the drift region. An insulated gate trench extends into the drift region. A diode region extends deeper into the drift region than the insulated gate trench and partly under the insulated gate trench so as to form a pn junction with the drift region below a bottom of the insulated gate trench. The body region adjoins a first sidewall of the insulated gate trench and the diode region adjoins a second sidewall of the insulated gate trench opposite the first sidewall so that the body region of the transistor cell and a channel region including a region of the body region extending along the first sidewall are separated from the diode region by the insulated gate trench.

公开(公告)号：US20170309484A1

公开(公告)日：2017-10-26

申请号：US15136573

申请日：2016-04-22

Applicant: Infineon Technologies AG

Inventor： Mihai Draghici ,  Romain Esteve ,  Craig Arthur Fisher ,  Gerald Unegg ,  Tobias Hoechbauer ,  Christian Heidorn

IPC: H01L21/225 ,  H01L21/311 ,  H01L21/027 ,  H01L21/02 ,  H01L21/324 ,  H01L21/04

CPC classification number: H01L21/2254 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0273 ,  H01L21/0455 ,  H01L21/31111 ,  H01L21/324 ,  H01L29/1608

Abstract: A method of defect reduction for a SiC layer includes activating dopants disposed in the SiC layer, depositing a carbon-rich layer on the SiC layer after activating the dopants, tempering the carbon-rich layer so as to form graphite on the SiC layer, and diffusing carbon from the graphite into the SiC layer. Carbon diffused from the graphite fills carbon vacancies in the SiC layer.

公开(公告)号：US09543414B2

公开(公告)日：2017-01-10

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L21/324 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

公开(公告)号：US09029974B2

公开(公告)日：2015-05-12

申请号：US14023819

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

IPC: H01L29/47 ,  H01L29/78 ,  H01L29/06 ,  H01L29/812 ,  H01L29/872

CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

公开(公告)号：US11842938B2

公开(公告)日：2023-12-12

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/76841 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/53223 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US11552172B2

公开(公告)日：2023-01-10

申请号：US16926695

申请日：2020-07-11

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Moriz Jelinek ,  Anton Mauder ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/40 ,  H01L29/08 ,  H01L21/04 ,  H01L29/872 ,  H01L29/739 ,  H01L29/04

Abstract: First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.