公开(公告)号：US11520555B2

公开(公告)日：2022-12-06

申请号：US17162864

申请日：2021-01-29

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  G06F3/147 ,  G06T1/20 ,  G09G5/36 ,  H04L65/402 ,  G09G3/00 ,  H04L67/131

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20220255559A1

公开(公告)日：2022-08-11

申请号：US17681364

申请日：2022-02-25

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US11283466B2

公开(公告)日：2022-03-22

申请号：US16563496

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Md. Mohiuddin Mazumder ,  Subas Bastola ,  Kai Xiao

IPC: H03M13/11 ,  G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US11276911B2

公开(公告)日：2022-03-15

申请号：US16164352

申请日：2018-10-18

Applicant: Intel Corporation

Inventor： Jingbo Li ,  Kai Xiao ,  Howard Heck ,  Kai Wang

IPC: H01P5/02 ,  H01B7/04 ,  H01P3/02 ,  H01R12/73 ,  H01P5/08 ,  H01R24/60

Abstract: In accordance with embodiments disclosed herein, there is provided a high-density low-loss cable and connector assembly. A cable assembly includes a first cable connector, a bulk cable section, and a first cable transition section. The bulk cable section includes a first plurality of conductive wires of a first wire thickness. The first cable transition section includes a second plurality of conductive wires that has a first distal end connected to the bulk cable section and a second distal end connected to the first cable connector. Each of the second plurality of conductive wires transitions from the first wire thickness at the first distal end to a second wire thickness that is less than the first wire thickness at the second distal end. Each of the second plurality of conductive wires in the first distal end is connected to a corresponding conductive wire of the first plurality of conductive wires.

公开(公告)号：US11106274B2

公开(公告)日：2021-08-31

申请号：US15483442

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Joydeep Ray ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Jefferson Amstutz ,  Carson Brownlee ,  Vivek Tiwari ,  Sayan Lahiri ,  Kai Xiao ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Deepak S. Vembar ,  Ankur N. Shah ,  Balaji Vembu ,  Josh B. Mastronarde

IPC: G06F3/01 ,  G06K9/00 ,  G06T1/20 ,  G06F3/048 ,  G06F3/0346

Abstract: An embodiment of a graphics apparatus may include a facial expression detector to detect a facial expression of a user, and a parameter adjuster communicatively coupled to the facial expression detector to adjust a graphics parameter based on the detected facial expression of the user. The detected facial expression may include one or more of a squinting, blinking, winking, and facial muscle tension of the user. The graphics parameter may include one or more of a frame resolution, a screen contrast, a screen brightness, and a shading rate. Other embodiments are disclosed and claimed.

公开(公告)号：US20210203094A1

公开(公告)日：2021-07-01

申请号：US17202961

申请日：2021-03-16

Applicant: Intel Corporation

Inventor： Xiang Li ,  Mo Liu ,  Shaohua Li ,  Jingbo Li ,  Kai Xiao

IPC: H01R12/73 ,  H01R12/57 ,  H01R12/72 ,  H01R13/26 ,  H05K1/18

Abstract: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.

公开(公告)号：US10922832B2

公开(公告)日：2021-02-16

申请号：US16050724

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Kai Xiao ,  Jill Boyce ,  Narayan Biswal ,  Jeffrey Tripp

IPC: G06K9/00 ,  G06T7/593 ,  G06T7/13 ,  G06T7/136 ,  G06T15/00 ,  G06T1/20 ,  G06T5/00

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first image projection into a plurality of regions, the plurality of regions comprising a plurality of points, determine an accuracy rating for the plurality of regions, and apply one of a first rendering technique to a first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions fails to meet an accuracy threshold or a second rendering technique to the first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions meets an accuracy threshold, and a memory communicatively coupled to the processor. Other embodiments may be described and claimed.

公开(公告)号：US20200292603A1

公开(公告)日：2020-09-17

申请号：US16799152

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Xiaoning Ye ,  Kai Xiao

IPC: G01R27/28

Abstract: Technologies for verifying a de-embedder for interconnect measurement include a verification compute device. The verification compute device is to measure a first signal transmitted through a single device under test and measure a second signal transmitted through a duplicated set of devices under test. Each device under test in the duplicated set is substantially identical to the single device under test. Additionally, the verification compute device is to apply a de-embedder to the measured first signal to remove an effect of test fixtures on the measured first signal, apply the de-embedder to the measured second signal to remove the effect of the test fixtures on the measured second signal, concatenate the de-embedded first signal with itself to generate a concatenated de-embedded first signal, and compare the concatenated de-embedded first signal with the de-embedded second signal to determine whether the concatenated de-embedded first signal matches the de-embedded second signal.

公开(公告)号：US20190287290A1

公开(公告)日：2019-09-19

申请号：US16271368

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Chandrasekaran Sakthivel ,  Michael Apodaca ,  Kai Xiao ,  Altug Koker ,  Jeffery S. Boles ,  Adam T. Lake ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  James M. Holland ,  Prasoonkumar Surti ,  Jonathan Kennedy ,  Louis Feng ,  Barnan Das ,  Narayan Biswal ,  Stanley J. Baran ,  Gokcen Cilingir ,  Nilesh V. Shah ,  Archie Sharma ,  Mayuresh M. Varerkar

IPC: G06T15/06 ,  G06F3/01 ,  H04S7/00 ,  G06T19/00 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems, apparatuses and methods may provide a way to selectively suppress and enhance VR/AR renderings of n-dimensional environments. The systems, apparatuses and methods may deepen a user's VR/AR experience by focusing on particular feedback information, while suppressing other feedback information from the environment.

公开(公告)号：US20190259128A1

公开(公告)日：2019-08-22

申请号：US16256441

申请日：2019-01-24

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Prasoonkumar Surti ,  Slawomir Grajewski ,  Louis Feng ,  Kai Xiao ,  Tomasz Janczak ,  Devan Burke ,  Travis T. Schluessler

IPC: G06T1/20 ,  G06T1/60

Abstract: An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.