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    SERVER RAS LEVERAGING MULTI-KEY ENCRYPTION
    21.
    发明申请
    SERVER RAS LEVERAGING MULTI-KEY ENCRYPTION 审中-公开

    公开(公告)号：US20190050283A1

    公开(公告)日：2019-02-14

    申请号：US16047638

    申请日：2018-07-27

    Applicant: Intel Corporation

    Inventor： David Durham ,  Siddhartha Chhabra ,  Kai Cong ,  Ron Gabor

    IPC: G06F11/07 ,  G06F3/06

    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.

    Byte level granularity buffer overflow detection for memory corruption detection architectures
    23.
    发明授权
    Byte level granularity buffer overflow detection for memory corruption detection architectures 有权

    公开(公告)号：US09766968B2

    公开(公告)日：2017-09-19

    申请号：US14668862

    申请日：2015-03-25

    Applicant: Intel Corporation

    Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor ,  Joseph Nuzman

    IPC: G06F11/07 ,  G06F11/10

    CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/10 ,  G06F11/1064

    Abstract: Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table. The processor can also include processor core coupled to the memory. The processor core can receive, from an application, a memory access request to access data of one or more contiguous memory blocks in a memory object of the memory. The processor core can also retrieve data stored in the one or more contiguous memory blocks based on the location indicated by the pointer. The processor core can also retrieve, from the MCD table, allocation information associated with the one or more contiguous memory blocks. The processor core can also send, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information.

    MEMORY WRITE PROTECTION FOR MEMORY CORRUPTION DETECTION ARCHITECTURES
    24.
    发明申请
    MEMORY WRITE PROTECTION FOR MEMORY CORRUPTION DETECTION ARCHITECTURES 有权
    用于存储器腐蚀检测架构的存储器写保护

    公开(公告)号：US20160371139A1

    公开(公告)日：2016-12-22

    申请号：US14745172

    申请日：2015-06-19

    Applicant: Intel Corporation

    Inventor： Tomer Stark ,  Ron Gabor ,  Ady Tal ,  Joseph Nuzman

    IPC: G06F11/07 ,  G06F11/16

    CPC classification number: G06F12/1425 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0787 ,  G06F11/1666 ,  G06F12/0238 ,  G06F2201/80 ,  G06F2212/1032

    Abstract: Memory corruption detection technologies are described. A processing system can include a processor core including a register to store an address of a memory corruption detection (MCD) table. The processor core can receive, from an application, a memory store request to store data in a first portion of a contiguous memory block of the memory object of a memory. The memory store request comprises a first pointer indicating a first location of the first portion in the memory block to store the data. The processor core can retrieve, from the MCD table, a write protection indicator that indicates a first protection mode of the first portion. The processor core can send, to the application, a fault message when a fault event associated with the first portion occurs based on the first protection mode of the first portion.

    Abstract translation: 描述了内存损坏检测技术。 处理系统可以包括处理器核心，其包括用于存储存储器破坏检测（MCD）表的地址的寄存器。 处理器核心可以从应用程序接收存储器存储请求，以将数据存储在存储器的存储器对象的连续存储器块的第一部分中。 存储器存储请求包括指示存储器块中的第一部分的第一位置以存储数据的第一指针。 处理器核心可以从MCD表中检索指示第一部分的第一保护模式的写保护指示符。 当基于第一部分的第一保护模式发生与第一部分相关联的故障事件时，处理器核心可以向应用发送故障消息。

    Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operations
    28.
    发明授权
    Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operations 有权

    公开(公告)号：US10725788B1

    公开(公告)日：2020-07-28

    申请号：US16363540

    申请日：2019-03-25

    Applicant: Intel Corporation

    Inventor： Jose Yallouz ,  Arkady Bramnik ,  Ron Gabor

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method includes calculating, by a processor core, a first residue code of a first packed vector stored in a first vector register of a set of vector registers; calculating a second residue code of a second packed vector stored in a second vector register of the set of vector registers; calculating, from an addition of the first residue code and the second residue code, a reference residue code for a SIMD arithmetic operation; performing an element-by-element execution of the SIMD arithmetic operation between data elements of the first packed vector and of the second packed vector, resulting in an output packed vector; calculating an output residue code of the output packed vector; and detecting an error in the SIMD arithmetic operation based on comparison of the reference residue code with the output residue code.

    Heap management for memory corruption detection
    29.
    发明授权
    Heap management for memory corruption detection 有权

    公开(公告)号：US10585741B2

    公开(公告)日：2020-03-10

    申请号：US16123933

    申请日：2018-09-06

    Applicant: Intel Corporation

    Inventor： Tomer Stark ,  Ady Tal ,  Ron Gabor

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.

    End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures
    30.
    发明授权
    End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures 有权

    公开(公告)号：US10346171B2

    公开(公告)日：2019-07-09

    申请号：US15402825

    申请日：2017-01-10

    Applicant: Intel Corporation

    Inventor： Ron Gabor ,  Yiannakis Sazeides ,  Arkady Bramnik

    IPC: G06F9/38 ,  G06F9/30 ,  G06F11/08

    Abstract: A processor of an aspect includes a plurality of physical storage locations, and a register rename unit. The register rename unit includes a first register rename storage structure that is to store a given physical storage location identifier, which is to identify a physical storage location of the plurality of physical storage locations, and that is to store a corresponding given one or more redundant bits. The register rename unit also includes a second register rename storage structure. The register rename unit also includes a first conductive path coupling the first and second register rename storage structures. The first conductive path is to convey the given one or more redundant bits end-to-end from the first register rename storage structure to the second register rename storage structure. Other processors are also disclosed, as well as methods and systems.

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