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公开(公告)号：US20250074766A1
公开(公告)日：2025-03-06
申请号：US18949864
申请日：2024-11-15
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
Abstract: A device includes a substrate and an intermetal dielectric (IMD) layer disposed over the substrate. The device also includes a first plurality of polysilicon layers disposed over the IMD layer and over a bumpstop. The device also includes a second plurality of polysilicon layers disposed within the IMD layer. The device includes a patterned actuator layer with a first side and a second side, wherein the first side of the patterned actuator layer is lined with a polysilicon layer, and wherein the first side of the patterned actuator layer faces the bumpstop. The device further includes a standoff formed over the IMD layer, a via through the standoff making electrical contact with the polysilicon layer of the actuator and a portion of the second plurality of polysilicon layers and a bond material disposed on the second side of the patterned actuator layer.
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公开(公告)号：US11952267B2
公开(公告)日：2024-04-09
申请号：US17584698
申请日：2022-01-26
Applicant: INVENSENSE, INC.
Inventor： Alan Cuthbertson , Daesung Lee
CPC classification number: B81C1/00166 , B81B3/001 , B81B3/0056 , B81B3/0089 , B81B2203/04 , B81C1/00031 , B81C2201/0166 , B81C2201/115
Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.
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公开(公告)号：US20230045563A1
公开(公告)日：2023-02-09
申请号：US17877207
申请日：2022-07-29
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
Abstract: A device includes a substrate comprising a first standoff, a second standoff, a third standoff, a first cavity, a second cavity, and a bonding material covering a portion of the first, the second, and the third standoff. The first cavity is positioned between the first and the second standoffs, and the second cavity is positioned between the second and the third standoffs. The first cavity comprises a first cavity region and a second cavity region separated by a portion of the substrate extruding thereto, and wherein a depth associated with the first cavity region is greater than a depth associated with the second cavity. A surface of the first cavity is covered with a getter material.
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Patent Agency Ranking
公开(公告)号：US20220380209A1
公开(公告)日：2022-12-01
申请号：US17334493
申请日：2021-05-28
Applicant: InvenSense, Inc.
Inventor： Ashfaque Uddin , Daesung Lee , Alan Cuthbertson
Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.
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公开(公告)号：US20220185662A1
公开(公告)日：2022-06-16
申请号：US17547388
申请日：2021-12-10
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
IPC: B81C1/00
Abstract: A method includes tab dicing a region of a tab region disposed between a first die and a second die. The tab region structurally connects the first die to the second die each including a MEMS device eutecticly bonded to a CMOS device. The tab region includes a handle wafer layer disposed over a fusion bond oxide layer that is disposed on an ACT layer. The tab region is positioned above a CMOS tab region that with the first and second die form a cavity therein. The tab dicing cuts through the handle wafer layer and leaves a portion of the fusion bond oxide layer underneath the handle wafer layer to form an oxide tether within the tab region. The oxide tether maintains the tab region in place and above the CMOS tab region. Subsequent to the tab dicing the first region, the tab region is removed.
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公开(公告)号：US20220144628A1
公开(公告)日：2022-05-12
申请号：US17584698
申请日：2022-01-26
Applicant: INVENSENSE, INC.
Inventor： Alan Cuthbertson , Daesung Lee
Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method can comprise forming a MEMS layer based on fusion bonding a handle MEMS with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.
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公开(公告)号：US20220106188A1
公开(公告)日：2022-04-07
申请号：US17195346
申请日：2021-03-08
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Alan Cuthbertson
Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.
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公开(公告)号：US20200262697A1
公开(公告)日：2020-08-20
申请号：US16795514
申请日：2020-02-19
Applicant: InvenSense, Inc.
Inventor： Daesung Lee , Ian Flader , Alan Cuthbertson , Emad Mehdizadeh
Abstract: Methods and systems for reducing stiction through roughening the surface and reducing the contact area in MEMS devices are disclosed. A method includes fabricating bumpstops on a surface of a MEMS device substrate to reduce stiction. Another method is directed to applying roughening etchant to a surface of a silicon substrate to enhance roughness after cavity etch and before removal of hardmask. Another embodiment described herein is directed to a method to reduce contact area between proof mass and UCAV (“upper cavity”) substrate surface with minimal impact on the cavity volume by introducing a shallow etch process step and maintaining high pressure in accelerometer cavity. Another method is described as to increasing the surface roughness of a UCAV substrate surface by depositing a rough layer (e.g. polysilicon) on the surface of the substrate and etching back the rough layer to transfer the roughness.
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