Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same
    21.
    发明授权
    Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same 有权
    半导体封装基板的电路阻挡结构及其制造方法

    公开(公告)号:US07012019B2

    公开(公告)日:2006-03-14

    申请号:US10876475

    申请日:2004-06-28

    Abstract: A circuit barrier structure of a semiconductor packaging substrate and a method for fabricating the same, forming a metal conductive layer on an insulating layer of the substrate and a patterned resist layer on the metal conductive layer. The patterned resist layer has a plurality of holes to expose predetermined parts of the metal conductive layer. A metal barrier layer is formed on the resist layer and in the holes. A patterned circuit layer is electroplated in the holes of the resist layer after removing the metal barrier layer on the resist layer. The resist layer and the metal conductive layer underneath the resist layer are removed. Another metal barrier layer can be formed on the circuit layer. The patterned circuit layer is covered by the metal barrier layers to prevent damage from etching to the circuit layer and inhibit migration of metal particles in the circuit layer.

    Abstract translation: 半导体封装基板的电路阻挡结构及其制造方法,在基板的绝缘层上形成金属导电层,在金属导电层上形成图案化的抗蚀剂层。 图案化的抗蚀剂层具有多个孔以暴露金属导电层的预定部分。 在抗蚀剂层和孔中形成金属阻挡层。 在除去抗蚀剂层上的金属阻挡层之后,在抗蚀剂层的孔中电镀图案化的电路层。 去除抗蚀剂层下面的抗蚀剂层和金属导电层。 可以在电路层上形成另一金属阻挡层。 图案化电路层被金属阻挡层覆盖,以防止腐蚀到电路层的损伤并且抑制金属颗粒在电路层中的迁移。

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