公开(公告)号：US10230424B2

公开(公告)日：2019-03-12

申请号：US14492143

申请日：2014-09-22

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Kishore Seendripu ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher

IPC: H04B1/40 ,  H04B1/74 ,  H04L25/02 ,  H04L27/20 ,  H04L27/22 ,  H04H60/19 ,  H04B1/00 ,  H04L27/36 ,  H04L27/38

Abstract: A monolithic integrated circuit for use in a microwave backhaul system may comprise a plurality of microwave transceivers and outdoor-unit to indoor-unit (ODU/IDU) interface circuitry. The monolithic integrated circuit may be configurable into an all-outdoor configuration in which the ODU/IDU interface circuitry is disabled. The monolithic integrated circuit may be configurable into a split-indoor-and-outdoor configuration in which the ODU/IDU interface circuitry is enabled to communicate signals between an outdoor unit of the microwave backhaul system and an indoor unit of the microwave backhaul system. While the monolithic integrated circuit is configured in the split-indoor-and-outdoor configuration, the ODU/IDU interface circuitry may be configurable to operate in at least a non-stacking mode and a stacking mode.

公开(公告)号：US20180183492A1

公开(公告)日：2018-06-28

申请号：US15904680

申请日：2018-02-26

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher

IPC: H04B1/74 ,  H04L27/36 ,  H04L27/20 ,  H04L27/38 ,  H04H60/19 ,  H04L25/02 ,  H04B1/40 ,  H04L27/22 ,  H04B1/00

CPC classification number: H04B1/745 ,  H04B1/0067 ,  H04B1/40 ,  H04H60/19 ,  H04L25/02 ,  H04L27/20 ,  H04L27/2003 ,  H04L27/22 ,  H04L27/36 ,  H04L27/362 ,  H04L27/38

Abstract: A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals.

公开(公告)号：US09941986B2

公开(公告)日：2018-04-10

申请号：US15297595

申请日：2016-10-19

Applicant: MaxLinear, Inc.

Inventor： Glenn Chang ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher ,  Shanta Murthy Prem Swaroop ,  Curtis Ling ,  Vamsi Paidi ,  Wenjian Chen

IPC: H04H40/90 ,  H04N21/61

CPC classification number: H04H40/90 ,  H04N21/6143

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

公开(公告)号：US09712886B2

公开(公告)日：2017-07-18

申请号：US15264060

申请日：2016-09-13

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Timothy Gallagher

IPC: H04J1/12 ,  H04B7/216 ,  H04L12/28 ,  H03H7/30 ,  H04N21/61 ,  H04N21/4385

CPC classification number: H04N21/6118 ,  H04L12/2801 ,  H04N21/4385 ,  H04N21/6168

Abstract: Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module. The triplexer may comprise a first port, a Multimedia Over Coaxial Alliance (MoCA) port, a television upstream port, and a television downstream port. The leakage processing module may comprise a television downstream input port, a cable television downstream output port, a MoCA port, and a cable television upstream port. The leakage processing module may be operable to (1) process a MoCA signal to generate a first compensation signal; (2) process a cable upstream signal to generate a second compensation signal; (3) process a filtered signal based at least in part on the first and second compensation signals; and (4) output the processed filtered signal via the cable television downstream output port of said leakage processing module.

公开(公告)号：US20170149399A1

公开(公告)日：2017-05-25

申请号：US14720637

申请日：2015-05-22

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Madhukar Reddy ,  John Wetherell

IPC: H03G3/20 ,  H04B1/16 ,  H04B17/318

CPC classification number: H03G3/20 ,  H03G3/3068 ,  H04B1/16 ,  H04B17/318

Abstract: An automatic gain control loop disposed in a receiver is adapted to compensate for varying levels of out of band interference sources by adaptively controlling the gain distribution throughout the receive signal path. One or more intermediate received signal strength indicator (RSSI) detectors are used to determine a corresponding intermediate signal level. The output of each RSSI detector is coupled to an associated comparator that compares the intermediate RSSI value against a corresponding threshold. The take over point (TOP) for gain stages is adjusted based in part on the comparator output values. The TOP for each of a plurality of gain stages may be adjusted in discrete steps or continuously.

公开(公告)号：US09509422B2

公开(公告)日：2016-11-29

申请号：US14948436

申请日：2015-11-23

Applicant: MaxLinear, Inc.

Inventor： Glenn Chang ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher ,  Shanta Murthy Prem Swaroop ,  Curtis Ling ,  Vamsi Paidi ,  Wenjian Chen

IPC: H04H40/90 ,  H04N21/61

CPC classification number: H04H40/90 ,  H04N21/6143

Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.

公开(公告)号：US09445149B2

公开(公告)日：2016-09-13

申请号：US14230058

申请日：2014-03-31

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Timothy Gallagher

IPC: H04J1/12 ,  H04B7/216 ,  H04L12/28 ,  H03H7/30 ,  H04N21/4385 ,  H04N21/61

CPC classification number: H04N21/6118 ,  H04L12/2801 ,  H04N21/4385 ,  H04N21/6168

Abstract: Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module. The triplexer may comprise a multiband port, a Multimedia Over Coaxial Alliance (MoCA) port, a television upstream port, and a television downstream port. The leakage processing module may comprise a television downstream input port, a cable television downstream output port, a MoCA port, and a cable television upstream port. The leakage processing module may be operable to (1) process a MoCA signal to generate a first compensation signal; (2) process a cable upstream signal to generate a second compensation signal; (3) process a filtered signal based at least in part on the first and second compensation signals; and (4) output the processed filtered signal via the cable television downstream output port of said leakage processing module.

Abstract translation: 提供了用于多频带通信系统的频带分离的方法和装置的方面。 在收发器中使用的一个或多个电路可以包括三工器和泄漏处理模块。 三工器可以包括多频带端口，多媒体同轴联盟（MoCA）端口，电视上行端口和电视下行端口。 泄漏处理模块可以包括电视下游输入端口，有线电视下游输出端口，MoCA端口和有线电视上行端口。 泄漏处理模块可操作为（1）处理MoCA信号以产生第一补偿信号; （2）处理电缆上行信号以产生第二补偿信号; （3）至少部分地基于第一和第二补偿信号来处理滤波信号; 和（4）经由所述泄漏处理模块的有线电视下游输出端口输出经处理的滤波信号。

公开(公告)号：US20160094266A1

公开(公告)日：2016-03-31

申请号：US14961987

申请日：2015-12-08

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raja Pullela ,  Madhukar Reddy ,  Timothy Gallagher

IPC: H04B1/40 ,  H04B1/74 ,  H04L27/38 ,  H04B1/00 ,  H04L27/36

CPC classification number: H04B1/745 ,  H04B1/0067 ,  H04B1/40 ,  H04H60/19 ,  H04L25/02 ,  H04L27/20 ,  H04L27/2003 ,  H04L27/22 ,  H04L27/36 ,  H04L27/362 ,  H04L27/38

Abstract: A microwave backhaul system may comprise a monolithic integrated circuit comprising an on-chip transceiver, digital baseband processing circuitry, and auxiliary interface circuitry. The on-chip transceiver may process a microwave signal from an antenna element to generate a first pair of quadrature baseband signals and convey the first pair of phase-quadrature baseband signals to the digital baseband processing circuitry. The auxiliary interface circuitry may receive one or more auxiliary signals from a source that is external to the monolithic integrated circuit and convey the one or more auxiliary signals to the digital baseband processing circuitry. The digital baseband processing circuitry may be operable to process signals to generate one or more second pairs of phase-quadrature digital baseband signals.

公开(公告)号：US20160088344A1

公开(公告)日：2016-03-24

申请号：US14948907

申请日：2015-11-23

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04N21/438 ,  H04B1/00 ,  H04N21/61 ,  H04N21/426 ,  H04N5/455 ,  H04N21/454

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a mixer module, a wideband analog-to-digital converter (ADC) module, and digital circuitry. The mixer module is configured to downconvert a plurality of frequencies that comprises a plurality of desired television channels and a plurality of undesired television channels. The wideband ADC module is configured to digitize the swatch of frequencies comprising the plurality of desired television channels and the plurality of undesired television channels. The digital circuitry is configured to select the desired plurality of television channels from the digitized plurality of frequencies, and output the selected plurality of television channels to a demodulator as a digital datastream.

公开(公告)号：US09210363B2

公开(公告)日：2015-12-08

申请号：US14617973

申请日：2015-02-10

Applicant: MaxLinear, Inc.

Inventor： Madhukar Reddy ,  Curtis Ling ,  Tim Gallagher

IPC: H04B1/16 ,  H04N5/50 ,  H04B1/00 ,  H04N21/426 ,  H04N21/438 ,  H04N21/454 ,  H04N21/61

CPC classification number: H04N21/4263 ,  H04B1/0014 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4382 ,  H04N21/4383 ,  H04N21/454 ,  H04N21/6143 ,  H04N21/6193

Abstract: A wideband receiver system comprises a wideband analog-to-digital converter (ADC) module and a digital frontend (DFE) module. The wideband ADC is configured to concurrently digitize a band of frequencies comprising a plurality of desired channels and a plurality of undesired channels. The DFE module is coupled to the digital in-phase and quadrature signals. The DFE module is configured to select the plurality of desired channels from the digitized band of frequencies, and generate an intermediate frequency (IF) signal comprising the selected plurality of desired channels and having a bandwidth that is less than a bandwidth of the band of frequencies, where the generation comprises frequency shifting of the selected plurality of desired channels. The IF signal may be a digital signal and the DFE is configured to output the IF signal via a serial or parallel interface.

Abstract translation: 宽带接收机系统包括宽带模数转换器（ADC）模块和数字前端（DFE）模块。 宽带ADC被配置为同时数字化包括多个期望信道和多个不期望信道的频带。 DFE模块耦合到数字同相和正交信号。 DFE模块被配置为从数字化的频带选择多个期望的信道，并且生成包括所选择的多个期望信道并且具有小于频带的带宽的带宽的中频（IF）信号 ，其中所述一代包括所选择的多个期望信道的频移。 IF信号可以是数字信号，并且DFE被配置为经由串行或并行接口输出IF信号。