Abstract:
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
Abstract:
A technique for controlling memory access ordering in a multi-processing system in which a sequence of accesses to acquire, access and release a shared space of memory is strictly adhered to by use of two specialized instructions for controlling memory access. Two instructions noted as MFDA (Memory Fence Directional--Acquire)and MFDR (Memory Fence Directional--Release) are utilized to control the ordering. The MFDA instruction when encountered in a program operates to ensure that all previous accesses to the specified address (typically to a lock controlling access to the shared space) become visible to other processors before all future accesses are permitted. The MFDR instruction when encountered in a program operates to ensure that all previous accesses become visible to other processors before any future accesses to the specified address. The accesses to the shared space of memory are then located between the MFDA and MFDR instructions and made visible to the other processors in proper order with respect to accesses for acquiring and releasing the shared space.
Abstract:
The invention provides a method and apparatus for providing operand reads in a processor pipeline. According to one aspect of the invention, a method is described for executing an instruction in a computer pipeline that requires different operands be read from the same register file in different stages of the computer pipeline. According to another aspect of the invention, a method is described for executing an instruction in a processor pipeline. According to this method, at least a first operand is read from a register file in a first stage of the processor pipeline. If execution of the instruction causes the processor to place the first operand in a storage area other than the register file, then the first operand in written to that storage area in a subsequent stage of the processor pipeline. Otherwise, one or more ALU operations are performed on the first operand and at least a second operand in a different subsequent stage of the processor pipeline.
Abstract:
A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
Abstract:
An adapter or bridging device that provides both a wired audio or audio and video female jack connectors for wired devices such as wired earphones, headphones and wired video headsets; as well as a wireless link to nearby handheld computerized devices such as mobile phones (e.g. smartphones). The device may be configured to be clipped to the user's clothing, as well as to interface with pairing control devices to easily form Bluetooth, WiFi, or other type wireless links. The device may also include at least one computer processor to manage the wireless link, control the attached wired headphones or video headsets, as well as perform compression and decompression functions as desired.
Abstract:
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
Abstract:
Method of controlling playback of Internet web page video on remote or high quality video displays using a remote control device, such as a smart phone. The method runs a first client browser on the remote control device, which in turn sends commands to a proxy browser with a data buffer. In response to user commands from the remote control device, the proxy browser retrieves and buffers video and non-video web page data from Internet servers, and sends this data to the remote control device. Upon user command, the proxy browser also sends selected buffered data to a second client browser that is connected to the remote or high quality video display. Media player playback commands on the remote control are echoed to a second media player on the second client browser, resulting in good synchronization between devices. Various compression, IP address adjustment, and public key methods are also discussed.
Abstract:
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed data element and a second packed data element are received from the first source register. A third packed data element and a fourth packed data element are received from the second source register. The circuit packs packing a portion of each of the packed data elements into a destination register resulting with the portion from second packed data element adjacent to the portion from the first packed data element, and the portion from the fourth packed data element adjacent to the portion from the third packed data element.
Abstract:
A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.
Abstract:
A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.