公开(公告)号：US20210202268A1

公开(公告)日：2021-07-01

申请号：US17124448

申请日：2020-12-16

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

Abstract: A package device and a manufacturing method thereof are provided. The manufacturing method of the package device includes providing a substrate and forming a redistribution layer on the substrate. The substrate has at least one device region and a non-device region. The redistribution layer includes at least one inspection structure and at least one wire structure. The wire structure is disposed in the device region, a part of the inspection structure and a part of the wire structure are formed of a same layer, and the inspection structure has a trench exposing the part of the inspection structure.

公开(公告)号：US20210074661A1

公开(公告)日：2021-03-11

申请号：US16740496

申请日：2020-01-13

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure including a circuit substrate, at least one chip, an encapsulant, a plurality of conductive connectors, a redistribution layer, and a plurality of conductive terminals is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least one chip has an active surface and a rear surface opposite to the active surface. The at least one chip is disposed on the circuit substrate with the rear surface. The encapsulant encapsulates the at least one chip. The plurality of conductive connectors surrounds the at least one chip. The redistribution layer is located on the encapsulant. The plurality of conductive terminals is located on the second surface. The at least one chip is electrically connected to the plurality of conductive terminals via the redistribution layer, the plurality of conductive connectors, and the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

公开(公告)号：US20210074645A1

公开(公告)日：2021-03-11

申请号：US16679326

申请日：2019-11-11

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Pei-Chun Tsai ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Nan-Chun Lin

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: A chip package structure using silicon interposer as interconnection bridge lifts multi-dies above the fan-out molding package embedded with premade Si interposer interconnection bridge under the multi-die space. The interconnection bridge connects the multi-dies through fine pitch high I/O interconnection. A first RDL and a second RDL are further disposed on top side and bottom side of the fan-out molding package, further providing connection for the multi-dies to a substrate via the connection routing inside the fan-out molding package.

公开(公告)号：US20210035936A1

公开(公告)日：2021-02-04

申请号：US16529796

申请日：2019-08-02

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure.

公开(公告)号：US20200328167A1

公开(公告)日：2020-10-15

申请号：US16698869

申请日：2019-11-27

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01Q1/22

Abstract: An integrated antenna package structure including a chip package and an antenna device is provided. The antenna device is disposed on the chip package. The chip package includes a chip, an encapsulant, a circuit layer, and a conductive connector. The encapsulant at least directly covers the back side of the chip. The circuit layer is disposed on the encapsulant and electrically connected to the chip. The conductive connector penetrates the encapsulant and is electrically connected to the circuit layer. The antenna device includes a dielectric body, a coupling layer, and an antenna layer. The dielectric body has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The coupling layer is disposed on the second dielectric surface of the dielectric body. The antenna layer is disposed on the first dielectric surface of the dielectric body. The antenna layer is electrically connected to the conductive connector. A manufacturing method of an integrated antenna package structure is also provided.

公开(公告)号：US20200328144A1

公开(公告)日：2020-10-15

申请号：US16382229

申请日：2019-04-12

Applicant: Powertech Technology Inc.

Inventor： Wen-Jeng Fan ,  Shang-Yu Chang Chien ,  Nan-Chun Lin ,  Hung-Hsin Hsu

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/66 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package including a semiconductor chip, a conductive element disposed aside the semiconductor chip, a conductive via disposed on and electrically connected to the conductive element, an insulating encapsulation, and a first circuit structure disposed on the semiconductor chip and the conductive via is provided. A height of the conductive element is less than a height of the semiconductor chip. The insulating encapsulation encapsulates the semiconductor chip, the conductive element, and the conductive via. The conductive via is located between the first circuit structure and the conductive element, and the semiconductor chip is electrically coupled to the conductive via through the first circuit structure.

公开(公告)号：US20200091103A1

公开(公告)日：2020-03-19

申请号：US16136197

申请日：2018-09-19

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.

公开(公告)号：US20190164888A1

公开(公告)日：2019-05-30

申请号：US16114237

申请日：2018-08-28

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien ,  Hung-Hsin Hsu ,  Nan-Chun Lin

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  H01L25/00

Abstract: A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.

公开(公告)号：US20190013283A1

公开(公告)日：2019-01-10

申请号：US15646055

申请日：2017-07-10

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： HIROYUKI FUJISHIMA ,  Shang-Yu Chang Chien

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L21/683

Abstract: A method of forming a Fan-Out Wafer Level semiconductor device includes forming only a plurality of metal bonding pads on a glass carrier. Electrode pads of a semiconductor chip are coupled to the plurality of metal bonding pads. The semiconductor chip and the plurality of metal bonding pads are encapsulated with a molding compound. The glass carrier can then be removed to expose a surface of the FOWLP structure. A redistribution layer is then formed on the exposed surface of the FOWLP structure. At least one metal trace within the redistribution layer is in electrical contact with the plurality of metal bonding pads. Solder balls may be mounted on the redistribution layer to provide electrical contact between the solder balls and the electrode pads of the semiconductor chip.

公开(公告)号：US20240313024A1

公开(公告)日：2024-09-19

申请号：US18523907

申请日：2023-11-30

Applicant: Powertech Technology Inc.

Inventor： Shang-Yu Chang Chien

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L27/14634 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure including a first redistribution circuit structure, a chip, a second redistribution circuit structure, a plurality of packages, and a plurality of limiting connectors is provided. The chip is disposed on the first redistribution circuit structure. The second redistribution circuit structure is disposed on the chip. The plurality of packages are disposed on the second redistribution circuit structure. Each of the packages includes an encapsulant. The plurality of limiting connectors are disposed between each of the packages and the second redistribution circuit structure.