Patent search ap:("RENESAS ELECTRONICS CORPORATION") AND inv:"Shinji BABA" Page 3

21.

发明申请
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开

公开(公告)号：US20170092614A1

公开(公告)日：2017-03-30

申请号：US15375072

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshihiro IWASAKI , Takeumi KATO , Takanori OKITA , Yoshikazu SHIMOTE , Shinji BABA , Kazuyuki NAKAGAWA , Michitaka KIMURA

IPC: H01L23/00 , H01L21/56 , H01L21/48

CPC classification number: H01L24/81 , H01L21/4853 , H01L21/563 , H01L23/49816 , H01L23/49838 , H01L24/03 , H01L24/04 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/75 , H01L24/83 , H01L24/94 , H01L25/043 , H01L25/0657 , H01L25/074 , H01L25/0756 , H01L25/117 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/0361 , H01L2224/03622 , H01L2224/03912 , H01L2224/0401 , H01L2224/051 , H01L2224/056 , H01L2224/1132 , H01L2224/1147 , H01L2224/1181 , H01L2224/11849 , H01L2224/11901 , H01L2224/131 , H01L2224/1403 , H01L2224/14104 , H01L2224/14131 , H01L2224/1605 , H01L2224/1701 , H01L2224/1703 , H01L2224/73204 , H01L2224/75252 , H01L2224/75745 , H01L2224/75824 , H01L2224/8101 , H01L2224/81024 , H01L2224/81048 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/81194 , H01L2224/81203 , H01L2224/81815 , H01L2224/81986 , H01L2224/831 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/3841 , H01L2224/81201 , H01L2924/00

Abstract: The joint reliability in flip chip bonding of a semiconductor device is enhanced. Prior to flip chip bonding, flux 9 is applied to the solder bumps 5a for flip chip bonding over a substrate and reflow/cleaning is carried out and then flip chip bonding is carried out. This makes is possible to thin the oxide film over the surfaces of the solder bumps 5a and make the oxide film uniform. As a result, it is possible to suppress the production of local solder protrusions to reduce the production of solder bridges during flip chip bonding and enhance the joint reliability in the flip chip bonding of the semiconductor device.

22.

发明申请
SEMICONDUCTOR DEVICE 有权
Title translation: 半导体器件

公开(公告)号：US20160027723A1

公开(公告)日：2016-01-28

申请号：US14871742

申请日：2015-09-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinji BABA , Toshihiro IWASAKI , Masaki Watanabe

IPC: H01L23/498 , H01L25/10 , H01L23/50

CPC classification number: H01L23/49816 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/00

Abstract: This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.

Abstract translation: 本发明提供作为低成本倒装芯片BGA的多引脚半导体器件。在倒装芯片BGA中，多层布线基板的上表面的周边区域中的多个信号接合电极被分离为内部和外部的多个信号接合电极，并且耦合到多个内部的信号布线耦合的多个信号通孔是位于多行信号键合电极和多个核心电源用接合电极之间的中心区域，使得可以减小芯片焊盘间距，并且能够在不增加数量的情况下降低BGA的成本的多层布线基板中的层。