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    Electro-optical phase modulator
    21.
    发明授权
    Electro-optical phase modulator 有权

    公开(公告)号：US11822164B2

    公开(公告)日：2023-11-21

    申请号：US17009468

    申请日：2020-09-01

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Stephane Monfray

    IPC: G02F1/025

    CPC classification number: G02F1/025 ,  G02F2202/06 ,  G02F2202/104 ,  G02F2202/105 ,  G02F2203/50

    Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

    Electronic circuit comprising a RF switches having reduced parasitic capacitances
    27.
    发明授权
    Electronic circuit comprising a RF switches having reduced parasitic capacitances 有权

    公开(公告)号：US12293981B2

    公开(公告)日：2025-05-06

    申请号：US17733589

    申请日：2022-04-29

    Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

    Inventor： Stephane Monfray ,  Siddhartha Dhar ,  Alain Fleury

    IPC: H01L23/66 ,  H01L21/48 ,  H01L23/373 ,  H01L23/42 ,  G11C13/00 ,  H10N70/00

    Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.

    Ion sensitive field effect transistor (ISFET) having higher sensitivity in response to dynamic biasing
    30.
    发明授权
    Ion sensitive field effect transistor (ISFET) having higher sensitivity in response to dynamic biasing 有权

    公开(公告)号：US10684251B2

    公开(公告)日：2020-06-16

    申请号：US15631078

    申请日：2017-06-23

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Getenet Tesega Ayele ,  Stephane Monfray

    IPC: G01N27/414

    Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.

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