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公开(公告)号：US20170248543A1
公开(公告)日：2017-08-31
申请号：US15251009
申请日：2016-08-30
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Gaspard Hiblot
IPC: G01N27/414 , H01L27/12 , H01L29/788 , H01L27/06 , H01L29/423
CPC classification number: H01L27/0722 , G01N27/414 , G01N27/4145 , G01N33/49 , G01R19/16519 , H01L27/0623 , H01L27/0705 , H01L27/1207 , H01L29/42356
Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.
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公开(公告)号：US09601382B2
公开(公告)日：2017-03-21
申请号：US14940325
申请日：2015-11-13
Inventor： Stephane Monfray , Ronald K. Sampson , Nicolas Loubet
IPC: H01L21/336 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/84 , H01L29/10 , H01L29/165 , H01L29/06
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
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公开(公告)号：US20150255705A1
公开(公告)日：2015-09-10
申请号：US14634454
申请日：2015-02-27
Applicant: STMicroelectronics SA , STMicroelectronics (Crolles 2) SAS
Inventor： Emilie Trioux , Pascal Ancey , Stephane Monfray , Thomas Skotnicki , Skandar Basrour , Paul Muralt
CPC classification number: H01L41/27 , B32B15/01 , C22F1/00 , C23C4/10 , C23C4/134 , C23C10/12 , F03G7/06 , H01L41/0805 , H01L41/0815 , H01L41/33 , Y10T29/42 , Y10T29/49005 , Y10T29/49124
Abstract: A method of manufacturing bistable strips having different curvatures, each strip including a plurality of portion of layers of materials, wherein at least one specific layer portion is deposited by a plasma spraying method in conditions different for each of the strips.
Abstract translation: 制造具有不同曲率的双稳态条带的方法，每条条带包括多个材料层，其中至少一个特定层部分通过等离子体喷涂方法在对每个条带不同的条件下进行沉积。
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公开(公告)号：US12293981B2
公开(公告)日：2025-05-06
申请号：US17733589
申请日：2022-04-29
Inventor： Stephane Monfray , Siddhartha Dhar , Alain Fleury
Abstract: The present disclosure relates to an electronic circuit comprising a semiconductor substrate, radiofrequency switches corresponding to MOS transistors comprising doped semiconductor regions in the substrate, at least two metallization levels covering the substrate, each metallization level comprising a stack of insulating layers, conductive pillars topped by metallic tracks, at least two connection elements each connecting one of the doped semiconductor regions and formed by conductive pillars and conductive tracks of each metallization level. The electronic circuit further comprises, between the two connection elements, a trench crossing completely the stack of insulating layers of one metallization level and further crossing partially the stack of insulating layers of the metallization level the closest to the substrate, and a heat dissipation device adapted for dissipating heat out of the trench.
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公开(公告)号：US20210041727A1
公开(公告)日：2021-02-11
申请号：US17083525
申请日：2020-10-29
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
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Patent Agency Ranking
公开(公告)号：US10823986B2
公开(公告)日：2020-11-03
申请号：US16254798
申请日：2019-01-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Frédéric Boeuf
Abstract: A photonic device includes a first region having a first doping type, and a second region having a second doping type, where the first region and the second region contact to form a vertical PN junction. The first region includes a silicon germanium (SiGe) region having a gradual germanium concentration.
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27.发明授权公开(公告)号：US10684251B2
公开(公告)日：2020-06-16
申请号：US15631078
申请日：2017-06-23
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Getenet Tesega Ayele , Stephane Monfray
IPC: G01N27/414
Abstract: A dual gate ion sensitive field effect transistor (ISFET) includes a first bias voltage node coupled to a back gate of the ISFET and a second bias voltage node coupled to a control gate of the ISFET. A bias voltage generator circuit is configured to generate a back gate voltage having a first magnitude and a first polarity for application to the first bias voltage node. The bias voltage generator circuit is further configured to generate a control gate voltage having a second magnitude and a second polarity for application to the second bias voltage node. The second polarity is opposite the first polarity.
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公开(公告)号：US10074649B2
公开(公告)日：2018-09-11
申请号：US15251009
申请日：2016-08-30
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Stephane Monfray , Gaspard Hiblot
IPC: H01L27/07 , G01N27/414 , H01L27/06 , H01L29/423 , G01R19/165 , G01N33/49
CPC classification number: H01L27/0722 , G01N27/414 , G01N27/4145 , G01N33/49 , G01R19/16519 , H01L27/0623 , H01L27/0705 , H01L27/1207 , H01L29/42356
Abstract: An integrated electronic detector operates to detecting a variation in potential on an input terminal. The detector includes a MOS transistor having a drain forming an output. Variation in drain current is representative of the variation in potential. A bipolar transistor has a base forming the input terminal and a collector electrically connected to the gate of the MOS transistor. The detector has a first configuration in which the bipolar transistor is conducting and the MOS transistor is turned off. The detector has a second configuration in which the bipolar transistor is turned off and the MOS transistor is in a sub-threshold operation. Transition of the detector from the first configuration to the second configuration occurs in response to the variation in potential.
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公开(公告)号：US09615443B2
公开(公告)日：2017-04-04
申请号：US14487758
申请日：2014-09-16
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics SA , Commissariat A L'Energie Atomique et aux Energies Alternatives
Inventor： Stephane Monfray , Sandrine Lhostis , Christophe Maitre , Olga Kokshagina , Philippe Coronel
IPC: F28F27/00 , H05K1/02 , F28D9/00 , F28F27/02 , H01L23/473
CPC classification number: H05K1/0203 , F28D9/0062 , F28F27/02 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit chip cooling device includes a network of micropipes. A first pipe portion and a second pipe portion of the network are connected by at least one valve. The valve is formed of a bilayer strip. In response to change in temperature, the shape of the bilayer strip changes to move the valve from a substantially closed position to an open position. In one configuration, the change is irreversible. In another configuration, the change is reversible in response to an opposite change in temperature.
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公开(公告)号：US09601381B2
公开(公告)日：2017-03-21
申请号：US14097565
申请日：2013-12-05
Inventor： Nicolas Loubet , Stephane Monfray , Ronald Kevin Sampson
IPC: H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/02 , H01L21/84 , H01L29/10 , H01L29/165 , H01L29/06
CPC classification number: H01L21/823431 , H01L21/02164 , H01L21/0217 , H01L21/02529 , H01L21/02532 , H01L21/02573 , H01L21/823418 , H01L21/823468 , H01L21/823481 , H01L21/845 , H01L29/0673 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.
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