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公开(公告)号：US20240250668A1
公开(公告)日：2024-07-25
申请号：US18100975
申请日：2023-01-24
Applicant: STMicroelectronics International N.V.
IPC: H03K3/037 , G01R31/3185 , G01R31/3187 , H03K19/20
CPC classification number: H03K3/037 , G01R31/318597 , G01R31/3187 , H03K19/20
Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.
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公开(公告)号：US11726140B2
公开(公告)日：2023-08-15
申请号：US17164570
申请日：2021-02-01
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Shiv Kumar Vats , Tripti Gupta
IPC: G01R31/3177 , G06F1/04 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31724 , G01R31/31727 , G06F1/04
Abstract: In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.
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公开(公告)号：US11680982B2
公开(公告)日：2023-06-20
申请号：US17510602
申请日：2021-10-26
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Manish Sharma , Tripti Gupta
IPC: G01R31/3177 , G01R31/317 , G06F1/28 , G01R31/3185 , G06F1/18
CPC classification number: G01R31/3177 , G01R31/31721 , G06F1/28 , G01R31/31723 , G01R31/318513 , G01R31/318536 , G01R31/318555 , G01R31/318558 , G01R31/318575 , G06F1/18
Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.
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公开(公告)号：US11557364B1
公开(公告)日：2023-01-17
申请号：US17443556
申请日：2021-07-27
Applicant: STMicroelectronics International N.V.
Abstract: Disclosed herein is logic circuitry and techniques for operation that hardware to enable the construction of first-in-first-out (FIFO) buffers from latches while permitting stuck-at-1 fault testing for the enable pin of those latches, as well as testing the data path at individual points through the FIFO buffer.
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公开(公告)号：US20220308610A1
公开(公告)日：2022-09-29
申请号：US17211545
申请日：2021-03-24
Applicant: STMicroelectronics International N.V.
Abstract: A method to bypass a voltage regulator of a system on a chip (SOC) comprising powering a first power domain using a voltage regulator; powering a second power domain using the voltage regulator; coupling a third power domain with an external voltage source; raising an external voltage supply from the external voltage source above a threshold level of the voltage regulator; coupling the first second power domains to the external voltage source; turning OFF the voltage regulator of the SOC after coupling the first power domain of the SOC and the second power domain of the SOC to the external voltage source; and powering the first power domain of the SOC, the second power domain of the SOC, and the third power domain of the SOC with the external voltage source, the external voltage source bypassing the voltage regulator.
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Patent Agency Ranking
公开(公告)号：US20220300389A1
公开(公告)日：2022-09-22
申请号：US17208935
申请日：2021-03-22
Applicant: STMicroelectronics International N.V.
IPC: G06F11/27 , G01R31/3177 , G06F1/08
Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
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公开(公告)号：US20190064270A1
公开(公告)日：2019-02-28
申请号：US15688184
申请日：2017-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan Srinivasan , Manish Sharma
IPC: G01R31/3185 , G06F11/267 , G06F11/27 , G01R31/3183
Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.
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公开(公告)号：US20240427366A1
公开(公告)日：2024-12-26
申请号：US18337720
申请日：2023-06-20
Applicant: STMicroelectronics International N.V.
IPC: G06F1/06
Abstract: According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.
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公开(公告)号：US20240264229A1
公开(公告)日：2024-08-08
申请号：US18165602
申请日：2023-02-07
Applicant: STMicroelectronics International N.V.
IPC: G01R31/317 , H03K19/0175
CPC classification number: G01R31/31721 , H03K19/017509
Abstract: According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.
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公开(公告)号：US12020760B2
公开(公告)日：2024-06-25
申请号：US18078714
申请日：2022-12-09
Applicant: STMicroelectronics International N.V.
CPC classification number: G11C29/38 , G11C7/1084 , G11C7/22 , G11C29/14 , G11C29/36 , G11C2029/1206 , G11C2029/3602 , H03K19/20
Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.
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