公开(公告)号：US20250126790A1

公开(公告)日：2025-04-17

申请号：US18756161

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minyong Lee ,  Jiyoung Kim ,  Sehoon Lee ,  Junhyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41 ,  H10B43/10 ,  H10B43/40

Abstract: An example non-volatile memory device includes a substrate including a first cell region, a second cell region, and a connection region between the first cell region and the second cell region, a mold structure including a plurality of gate electrodes being stacked in a stepped pattern in a pad region, a trench along a profile of the mold structure on the pad region, the trench including a bottom surface having a stair shape and a first sidewall on a boundary between the pad region and a wall region, a liner film on the first sidewall of the trench, a recess in the trench and exposing a pad portion of a gate electrode, a cell contact provided at the recess and connected with the pad portion, and a cover insulating layer provided at the trench. The liner film has a different etch selectivity with respect to the cover insulating layer.

公开(公告)号：US20250048636A1

公开(公告)日：2025-02-06

申请号：US18652120

申请日：2024-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bumkyu Kang ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27

Abstract: A semiconductor device includes a first semiconductor structure including a substrate, circuit elements, and circuit interconnection lines, and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure includes a plate layer, first gate electrodes stacked on the plate layer and spaced apart from each other in a first direction, separation regions penetrating through the first gate electrodes and extending in a second direction, first channel structures spaced apart from the separation regions in a third direction, penetrating through the first gate electrodes, and extending in the first direction, and dummy structures contacting the separation regions, penetrating through the first gate electrodes, and extending in the first direction. The first channel structures and the dummy structures respectively have a circular shape in plan view, and the separation regions are in contact with at least portions of respective side surfaces of the dummy structures.

公开(公告)号：US20240237362A9

公开(公告)日：2024-07-11

申请号：US18323440

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.

公开(公告)号：US20240164101A1

公开(公告)日：2024-05-16

申请号：US18355450

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a second substrate, a stack structure between the second substrate and the peripheral circuit structure and including interlayer dielectric layers and conductive patterns that are stacked alternately with the interlayer dielectric layers, vertical channel structures that include respective portions the stack structure and include vertical semiconductor patterns, respectively, and connection vias that include respective portions the second substrate and are connected to respective top surfaces of the vertical semiconductor patterns.

公开(公告)号：US20240138157A1

公开(公告)日：2024-04-25

申请号：US18323440

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.

公开(公告)号：US20240049480A1

公开(公告)日：2024-02-08

申请号：US18120038

申请日：2023-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Dohyung Kim ,  Jiwon Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device may include a first semiconductor structure including a lower substrate; and a second semiconductor structure on and bonded to the first semiconductor structure through a bonding structure. The second semiconductor structure may include: a pattern structure; an upper insulating layer on the pattern structure; a stack structure including gate electrode layers and interlayer insulating layers alternately stacked between the first semiconductor structure and the pattern structure; channel structures that extend through the stack structure; separation structures that extend through the stack structure and separate the stack structure. Each of the separation structures may include a first portion that extends through the stack structure and a second portion that extends from the first portion and extends through the pattern structure, and the second semiconductor structure further may include a spacer layer that separates the second portion of each separation structure from the pattern structure.

公开(公告)号：US20240008274A1

公开(公告)日：2024-01-04

申请号：US18178114

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L29/423 ,  H01L23/528 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/27 ,  H01L29/42328 ,  H01L29/42344 ,  H01L23/5283 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

Abstract: An integrated circuit device includes a semiconductor substrate, and a common source structure on the substrate. A vertical stack of memory cell gate electrodes is provided, which extends between the common source structure and the substrate. The vertical stack of memory cell gate electrodes includes a first erase control gate electrode, and a plurality of word lines extending between the first erase control gate electrode and the substrate. At least one channel structure is provided, which vertically penetrates through the vertical stack of memory cell gate electrodes. A source protrusion pattern is provided, which is electrically connected to the common source structure. The source protrusion pattern extends sufficiently through the vertical stack of memory cell gate electrodes that a portion of the source protrusion pattern extends opposite a sidewall of the first erase control gate electrode.

公开(公告)号：US11838398B2

公开(公告)日：2023-12-05

申请号：US18051138

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonju Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Seuk Son ,  Sooeun Lee ,  Dongchul Choi

IPC: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K5/00

CPC classification number: H04L7/033 ,  H03K3/037 ,  H03K5/26 ,  H03K2005/00286

Abstract: A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

公开(公告)号：US20230170302A1

公开(公告)日：2023-06-01

申请号：US17934743

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo Gu ,  Jiyoung Kim ,  Woosung Yang ,  Sukkang Sung ,  Chang-Sup Lee

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: Disclosed are semiconductor devices and electronic systems including the same. A semiconductor device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes and dielectric layers that are stacked in alternating fashion, each of the plurality of electrodes including an electrode part on the cell array region and a pad part on the connection region, dummy vertical structures on the connection region and penetrating the pad parts of each of the electrodes, and a cell contact plug on the connection region and coupled to the pad part of each of the electrodes. A thickness of the pad part is greater than that of the electrode part. The pad part has a lower portion connected to the electrode part and an upper portion on the lower portion. Between adjacent ones of the dummy vertical structures, a width of the upper portion is not less than that of the lower portion.

公开(公告)号：US11637110B2

公开(公告)日：2023-04-25

申请号：US17580811

申请日：2022-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihye Kim ,  Jaehoon Lee ,  Jiyoung Kim ,  Bongtae Park ,  Jaejoo Shim

IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/112 ,  H01L27/11585 ,  H01L27/32 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.