公开(公告)号：US20210234016A1

公开(公告)日：2021-07-29

申请号：US17227456

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngtek OH ,  Jinwook JUNG ,  Seunggeol NAM ,  Wontaek SEO ,  Insu JEON

IPC: H01L29/45

Abstract: Provided are transistors including an electride electrode. The transistor includes a substrate, a source region and a drain region doped with ions of different polarity from the substrate in a surface of the substrate, a source electrode and a drain electrode including an electride material on the source region and the drain region, a gate insulating layer surrounding the source electrode and a drain electrode on the substrate, and a gate electrode between the source electrode and the drain electrode on the substrate. The source electrode and the drain electrode have an ohmic contact with the substrate.

公开(公告)号：US20160155683A1

公开(公告)日：2016-06-02

申请号：US14955112

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Seunggeol NAM ,  Hyeonjin SHIN ,  Haeryong KIM ,  Seongjun PARK

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3128 ,  H01L23/3731 ,  H01L23/4334 ,  H01L23/49816 ,  H01L2224/141 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor package includes a semiconductor chip on a substrate, a thermal conductive film on a lower surface of the semiconductor chip, the thermal conductive film facing the substrate, and a molding member on the substrate and surrounding a sidewall of the semiconductor chip.

Abstract translation: 半导体封装包括：衬底上的半导体芯片，半导体芯片的下表面上的导热膜，与衬底相对的导热膜，以及在衬底上的模制构件，并且围绕半导体芯片的侧壁。

公开(公告)号：US20250126875A1

公开(公告)日：2025-04-17

申请号：US18913129

申请日：2024-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Seunggeol NAM ,  Donghoon KIM ,  Sijung YOO ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: Provided is a semiconductor device including a channel layer including a semiconductor material, a ferroelectric layer arranged on the channel layer and including a ferroelectric material, a gate electrode arranged on the ferroelectric layer, a first insertion layer arranged between the ferroelectric layer and the gate electrode and including a first paraelectric material, and a second insertion layer arranged between the channel layer and the ferroelectric layer and including a second paraelectric material having a dielectric constant higher than a dielectric constant of the first paraelectric material.

公开(公告)号：US20250107208A1

公开(公告)日：2025-03-27

申请号：US18976637

申请日：2024-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Seunggeol NAM ,  Keunwook SHIN ,  Dohyun LEE

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

公开(公告)号：US20240172447A1

公开(公告)日：2024-05-23

申请号：US18491161

申请日：2023-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Hyunjae LEE ,  Dukhyun CHOE

IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: Provided is a three-dimensional (3D) ferroelectric memory device. The 3D ferroelectric memory device includes a substrate, a plurality of insulating layers stacked on the substrate, a plurality of gate electrodes between the plurality of insulating layers, a plurality of gate insulating layers in contact with the plurality of gate electrodes, a plurality of intermediate electrodes in contact with the plurality of gate insulating layers, a ferroelectric layer in contact with the plurality of intermediate electrodes and the plurality of insulating layers, and a channel layer in contact with the ferroelectric layer.

公开(公告)号：US20230275150A1

公开(公告)日：2023-08-31

申请号：US18168699

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE

IPC: H01L29/78 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L29/7606

Abstract: A semiconductor device may include a semiconductor substrate including a dopant having a polarity; a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite to a polarity of the semiconductor substrate; a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. A doping concentration of the semiconductor substrate may be less than a concentration of the majority carrier of the channel layer.

公开(公告)号：US20230153592A1

公开(公告)日：2023-05-18

申请号：US18053182

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hagyoul Bae ,  Jinseong Heo

IPC: G06N3/063 ,  H10B51/30 ,  H10B51/20 ,  G11C11/54 ,  G11C11/22

CPC classification number: G06N3/063 ,  H01L27/1159 ,  H01L27/11597 ,  G11C11/54 ,  G11C11/223 ,  G11C11/2255 ,  G11C11/2257

Abstract: A ferroelectric memory device may include a source, a drain, a channel layer between the source and the drain and connected to the source and the drain, a first gate electrode and a second gate electrode located on the channel layer to be spaced apart from each other, and a ferroelectric layer between the channel layer and the first gate electrode and between the channel layer and the second gate electrode. Different voltages may be applied to the first gate electrode and the second gate electrode.

公开(公告)号：US20230041352A1

公开(公告)日：2023-02-09

申请号：US17565807

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Seunggeol NAM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L23/528 ,  H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure may include a dielectric layer including a trench; a conductive line in the trench; and a first cap layer on an upper surface of the conductive line. The first cap layer may include a graphene-metal composite including graphene and a metal mixed with each other.

公开(公告)号：US20230009791A1

公开(公告)日：2023-01-12

申请号：US17545442

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yunseong LEE ,  Jinseong HEO ,  Taehwan MOON ,  Seunggeol NAM ,  Dukhyun CHOE

IPC: H01L29/51 ,  H01L27/11502 ,  H01L27/11585

Abstract: A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an antiferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

公开(公告)号：US20220262903A1

公开(公告)日：2022-08-18

申请号：US17735475

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Haeryong KIM ,  Hyeonjin SHIN ,  Seunggeol NAM ,  Seongjun PARK

IPC: H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/417 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.