公开(公告)号：US20030146519A1

公开(公告)日：2003-08-07

申请号：US10192399

申请日：2002-07-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang

IPC: H01L023/48

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/3738 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A FCBGA (flip-chip ball grid array) semiconductor package with a heat-dissipating device and a method for fabricating the same are provided. At least a chip is mounted on a substrate in a flip-chip manner, and connected to a heat-dissipating device that is composed of a heat sink and a plurality of thermally conductive bumps implanted on the beat sink. Heat produced from the chip is dissipated via the heat-dissipating device. The thermally conductive bumps are bonded to a circuit board, and thereby reduce contact area between the heat-dissipating device and the circuit board, without forming of voids or popcorn effect during a solder-reflow process. The heat sink in contact with the chip is similar in coefficient of thermal expansion (CTE) to the chip, so as to prevent delamination between the heat sink and the chip, thereby assuring quality and yield of fabricated package products.

Abstract translation: 提供了具有散热装置的FCBGA（倒装球栅阵列）半导体封装及其制造方法。 至少芯片以倒装芯片方式安装在基板上，并且连接到由散热器和植入在节流槽上的多个导热凸块组成的散热装置。 从芯片产生的热量通过散热装置消散。 导热凸块接合到电路板上，从而减少了散热装置与电路板之间的接触面积，而不会在焊料回流过程中形成空隙或爆米花效应。 与芯片接触的散热片的热膨胀系数（CTE）与芯片相似，以防止散热片与芯片之间的分层，从而确保制造的封装产品的质量和产量。

公开(公告)号：US20030124834A1

公开(公告)日：2003-07-03

申请号：US10075043

申请日：2002-02-12

Applicant: Siliconware Precision Industries Co., Ltd.,

Inventor： David Tseng ,  Chien-Ping Huang ,  Kun-Ming Huang

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L22/20 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/45144 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/48 ,  H01L2924/00015 ,  H01L2224/05599

Abstract: A method and a system of wire bonding for use in semiconductor package fabrication are proposed. When one wire-bonded substrate unit of a substrate mounted with chips is introduced into a testing region, a next adjacent substrate unit is simultaneously formed with bonding wires in a wire-bonding region. In the testing region, the wire-bonded substrate unit is tested for wire bonding quality. If no wire opening or short occurs, the wire-bonded substrate unit is readily used for subsequent package fabrication. If wire opening or short is detected, a controlling module associated with the testing region generates a control signal to the wire-bonding region for interrupting a wire-bonding process, whereby causes of wire opening or short are overcome, and defective bonding wires are reworked. Therefore, inferiors or malfunction is timely detected, making overall fabrication process more time-effectively implemented; and inferiors are reworked for later usage, thereby significantly reducing fabrication costs.

Abstract translation: 提出了一种用于半导体封装制造的引线接合方法和系统。 当安装有芯片的基板的一个引线键合衬底单元被引入到测试区域中时，下一个相邻的衬底单元在引线接合区域中同时形成有接合线。 在测试区域中，对引线键合衬底单元进行线焊接质量测试。 如果没有发生导线开路或短路，则线接合基板单元容易用于随后的封装制造。 如果检测到电线断路或短路，则与测试区域相关联的控制模块产生对引线接合区域的控制信号，用于中断引线接合工艺，从而克服导线开路或短路的原因，并且对焊接线进行重新加工 。 因此，及时检测到下级或故障，使整体制作过程更加时间有效地实现; 并且为了稍后的使用而改造下层，从而显着降低制造成本。

公开(公告)号：US20020121705A1

公开(公告)日：2002-09-05

申请号：US09973611

申请日：2001-10-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Han-Ping Pu ,  Shih-Kuang Chiu ,  Keng-Yuan Liao ,  Chien-Ping Huang

IPC: H01L023/48

CPC classification number: H01L23/3128 ,  H01L23/4334 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Abstract translation: 提出了一种倒装芯片半导体封装，其中，堤坝结构由围绕芯片的基板上的诸如环氧树脂的粘合剂化合物形成。 粘合剂化合物的热膨胀系数比基板的热膨胀系数大，并且在制造冷却过程中产生较大的热收缩力，以抵消基板的热应力，从而保持基板和芯片的平面性和结构完整性 。 此外，芯片可以以将非活性表面暴露于大气中以便于散发由芯片产生的热量的方式制造，同时可以在芯片上另外设置散热器，从而进一步改善热量 耗散半导体封装的效率。

公开(公告)号：US20020117764A1

公开(公告)日：2002-08-29

申请号：US09796164

申请日：2001-02-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang

IPC: H01L023/28

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K1/0203 ,  H05K3/341 ,  H01L2224/05599

Abstract: A lead-on-chip (LOC) type of semiconductor package is proposed, which is characterized by the provision of an embedded heat sink in the encapsulation body and thermally coupled to the packaged semiconductor chip. The proposed semiconductor package is constructed on a leadframe including an outer-lead portion, an inner-lead portion, and a downset bond-finger portion. During packaging process, a semiconductor chip is arranged on the back side of the inner-lead portion of the leadframe and whose active surface is attached to the downset bond-finger portion of the leadframe; then, a plurality of bonding wires are bonded between the respective I/O pads of the semiconductor chip and the downset bond-finger portion of the leadframe. Further, a heat sink is adhered to the front side of the inner-lead portion of the leadframe by means of an electrically-insulative and thermally-conductive adhesive material. Finally, an encapsulation body is formed to encapsulate the semiconductor chip, the inner-lead portion of the leadframe, the bonding wires, and the heat sink. Owing to the embedded heat sink configuration, it allows the packaged semiconductor chip to have good heat-dissipation efficiency during operation and also allows the overall package body to be made very compact in size.

Abstract translation: 提出了片上芯片（LOC）类型的半导体封装，其特征在于在封装体中提供嵌入式散热器并热耦合到封装的半导体芯片。 所提出的半导体封装构造在包括外引线部分，内引线部分和降低焊接指部分的引线框架上。 在包装过程中，半导体芯片布置在引线框架的内引线部分的背面，并且其有源表面附着到引线框架的下端接合指部分; 然后，多个接合线接合在半导体芯片的各个I / O焊盘和引线框的下端接合指部之间。 此外，借助于电绝缘导热粘合剂材料将散热片附接到引线框架的内引线部分的前侧。 最后，形成封装本体以封装半导体芯片，引线框的内引线部分，接合线和散热片。 由于嵌入式散热器配置，它允许封装的半导体芯片在操作期间具有良好的散热效率，并且还允许整体封装体的尺寸非常紧凑。

公开(公告)号：US20020089832A1

公开(公告)日：2002-07-11

申请号：US10047498

申请日：2001-10-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang

IPC: H01L023/28 ,  H01L023/12 ,  H05K007/06

CPC classification number: H05K5/0095 ,  H01L21/565 ,  H01L23/552 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package with a flash-proof device is proposed, in which at least one chip and at least one passive device mounted on a substrate are covered by a flash-proof device dimensionally designed for positioning the substrate in a conventional mold and preventing a molding resin from flashing on the substrate in a molding process, and thus quality of the fabricated package can be assured. Due to no need of a specifically designed mold, fabrication costs are reduced. Furthermore, the flash-proof device has its top side exposed to outside of an encapsulant formed in the molding process, thereby allowing heat dissipating efficiency to be improved. Moreover, the flash-proof device provides shielding for the chip and the passive device received therein, so that external electromagnetic interference with performance of the semiconductor package can be reduced.

Abstract translation: 提出了一种具有防闪光装置的半导体封装件，其中安装在基板上的至少一个芯片和至少一个无源器件被尺寸设计用于将基板定位在常规模具中并防止成型的防闪光器件覆盖 树脂在模制过程中在衬底上闪烁，从而可以确保制造的包装的质量。 由于不需要专门设计的模具，制造成本降低。 此外，防闪光装置的顶面暴露于在成型工序中形成的密封剂的外侧，从而能够提高散热效率。 此外，防闪光装置为芯片和其中接收的无源装置提供屏蔽，从而可以减少与半导体封装的性能的外部电磁干扰。

公开(公告)号：US20020079570A1

公开(公告)日：2002-06-27

申请号：US09924049

申请日：2001-08-07

Applicant: Siliconware Precision Industries Co., Ltd,

Inventor： Tzong-Da Ho ,  Chien-Ping Huang ,  Yu-Po Wang

IPC: H01L023/48

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package with a heat dissipating element is proposed, in which the contact area between a semiconductor chip and the heat dissipating element is significantly reduced as the chip merely has its edge portion attached to the dissipating element. This makes an effect of a thermal stress on the chip reduced so as to prevent cracking and delamination for the chip. Moreover, the chip is partially exposed to the atmosphere, which allows the efficiency of heat dissipation and moisture escapement to be improved, so as to prevent a popcorn effect from occurrence and make the semiconductor package assured in reliability and quality.

Abstract translation: 提出了具有散热元件的半导体封装，其中半导体芯片和散热元件之间的接触面积显着减小，因为芯片仅将其边缘部分附接到散热元件。 这使得芯片上的热应力降低，从而防止芯片的开裂和分层。 此外，芯片部分地暴露于大气中，这样可以提高散热效果和水分擒纵性，从而防止爆米花效应的发生，从而确保半导体封装的可靠性和质量。

公开(公告)号：US20040227234A1

公开(公告)日：2004-11-18

申请号：US10618011

申请日：2003-07-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chien-Ping Huang

IPC: H01L023/48

CPC classification number: H01L23/13 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L31/0203 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2924/15311 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A flash-preventing window ball grid array semiconductor package, a method for fabricating the same, and a chip carrier used in the semiconductor package are provided. The chip carrier has a through hole and has a surface formed with a plurality of wire-bonding portions, ball-bonding portions and intended-exposing regions. A chip is mounted over the through hole and electrically connected to the wire-bonding portions by a plurality of bonding wires penetrating through the through hole. An encapsulation body encapsulates the chip and bonding wires. The intended-exposing regions serve as a narrow runner which is filled with an encapsulating material forming the encapsulation body, making the encapsulating material not flash over the ball-bonding portions. This allows a plurality of solder balls to be well bonded to the ball-bonding portions, thereby assuring the quality of electrical connection and the surface planarity of the semiconductor package.

Abstract translation: 提供防闪光窗球栅阵列半导体封装，其制造方法以及半导体封装中使用的芯片载体。 芯片载体具有通孔，并且具有形成有多个引线接合部分，滚珠接合部分和预期曝光区域的表面。 芯片安装在通孔上方，并通过贯穿通孔的多根接合线电连接到引线接合部分。 封装体封装芯片和接合线。 预期曝光区域用作填充有形成封装体的封装材料的窄流道，使得封装材料不会在滚珠焊接部分上闪烁。 这允许多个焊球与滚珠焊接部分良好地结合，从而确保电连接的质量和半导体封装的表面平面度。

公开(公告)号：US20030230792A1

公开(公告)日：2003-12-18

申请号：US10196305

申请日：2002-07-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Chuan Wu ,  Chien-Ping Huang ,  Han-Ping Pu

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50 ,  H01L023/495

CPC classification number: H01L24/16 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49575 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00

Abstract: A flip-ship semiconductor package with a lead frame as a chip carrier is provided, wherein a plurality of leads of the lead frame are each formed with at least a dam member thereon. When a chip is mounted on the lead frame by means of solder bumps, each of the solder bumps is attached to the corresponding one of the leads at a position between the dam member and an inner end of the lead. During a reflow-soldering process for wetting the solder bumps to the leads, the dam members would help control collapse height of the solder bumps, so as to enhance resistance of the solder bumps to thermal stress generated by CTE (coefficient of thermal expansion) mismatch between the chip and the leads, thereby preventing incomplete electrical connection between the chip and the leads.

Abstract translation: 提供一种具有引线框架作为芯片载体的翻转半导体封装，其中引线框架的多个引线至少形成有至少一个阻挡构件。 当通过焊料凸块将芯片安装在引线框架上时，每个焊料凸块在引线的阻挡件和引线的内端之间的位置附接到相应的一个引线。 在用于将焊料凸点润湿到引线的回流焊接过程中，阻挡构件将有助于控制焊料凸块的塌陷高度，从而增强焊料凸块对CTE产生的热应力的阻力（热膨胀系数）不匹配 在芯片和引线之间，从而防止芯片和引线之间的不完全的电连接。

公开(公告)号：US20030092205A1

公开(公告)日：2003-05-15

申请号：US10060564

申请日：2002-01-30

Applicant: Siliconware Precision Industries, Co., Ltd.

Inventor： Chi-Chuan Wu ,  Chien-Ping Huang

IPC: H01L021/66 ,  H01L023/495 ,  H01L023/48 ,  H01L023/34 ,  H01L029/40 ,  H01L023/28

CPC classification number: H01L24/33 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/484 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A QFN semiconductor package and a fabrication method thereof are proposed, wherein a lead frame having a plurality of leads is adopted, and each lead is formed at its inner end with a protruding portion. A wire bonding region and a bump attach region are respectively defined on opposite surfaces of the protruding portion, and staggered in position. This allows a force applied from a wire bonder to the wire bonding regions not to adversely affect solder bumps implanted on the bump attach regions, so that the solder bumps can be structurally assured without cracking. Moreover, the wire bonding regions spaced apart from the bump attach regions can be prevented from being contaminated by an etching solution used in solder bump implantation, so that wire bonding quality can be well maintained.

Abstract translation: 提出了一种QFN半导体封装及其制造方法，其中采用具有多个引线的引线框架，并且每个引线的内端形成有突出部分。 引线接合区域和突起附着区域分别限定在突出部分的相对表面上并且交错位置。 这允许从引线接合器施加到引线接合区域的力不会不利地影响注入在凸块附接区域上的焊料凸起，使得焊料凸块可以在结构上确保而不会破裂。 此外，可以防止与凸块附接区域间隔开的引线接合区域被焊料凸块注入中使用的蚀刻溶液污染，从而可以良好地保持引线接合质量。

公开(公告)号：US20020180024A1

公开(公告)日：2002-12-05

申请号：US09982347

申请日：2001-10-18

Applicant: Siliconware Precision Industries Co., Ltd., Taiwan R.O.C.

Inventor： Chien-Ping Huang ,  Tzong-Da Ho

IPC: H01L023/02

CPC classification number: H01L21/565 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor package and a method for fabricating the same are proposed, wherein, in a molding process for encapsulating a semiconductor chip mounted on a substrate, a mold is used with a molding cavity formed with a plurality of recess portions relatively smaller in height, and with a plurality of air vents for connecting the recess portions to outside of the mold and for ventilate air in the molding cavity. This allows a molding resin used during molding to slow down its flow when flowing into the recess portions, as the molding resin rapidly absorbs heat transmitted from the mold and is increased in viscosity thereof. The slowed down molding resin can therefore be prevented from flashing out of the air vents, so that quality and appearance of the fabricated semiconductor package can be well assured.

Abstract translation: 提出了一种半导体封装及其制造方法，其中，在用于封装安装在基板上的半导体芯片的模制工艺中，使用具有形成有相对较小高度的多个凹部的模腔，并且 具有用于将凹部连接到模具外部并用于使模制空腔中的空气通风的多个通风口。 这样，当模制树脂快速吸收从模具传递的热量并且其粘度增加时，这允许在模制期间使用的模塑树脂在流入凹部时减慢其流动。 因此，可以防止减速模制树脂从通风孔中闪出，从而可以很好地确保制造的半导体封装的质量和外观。