公开(公告)号：US20240372553A1

公开(公告)日：2024-11-07

申请号：US18773777

申请日：2024-07-16

Applicant: Texas Instruments Incorporated

Inventor： Robin Hoel ,  Anuvrat Srivastava ,  Aniruddha P N ,  Anand Kumar G

IPC: H03K21/10 ,  G06F1/08 ,  G06F1/10

Abstract: An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.

公开(公告)号：US20240275283A1

公开(公告)日：2024-08-15

申请号：US18169014

申请日：2023-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Rinu MATHEW ,  Vineet KHURANA ,  Anand Kumar G ,  Aniruddha PERIYAPATNA NAGENDRA ,  Harikrishna PARTHASARATHY

IPC: H02M3/158 ,  H02J7/00

CPC classification number: H02M3/158 ,  H02J7/007 ,  H02J2207/20

Abstract: In an example, a voltage converter includes a pulse generator. The voltage converter also includes a high-side transistor having a gate coupled to the pulse generator, a source coupled to a first voltage terminal, and a drain coupled to an output node. The voltage converter includes a low-side transistor having a gate coupled to the pulse generator, a source coupled to a second voltage terminal, and a drain coupled to the output node. The voltage converter includes a charge lookup table coupled to the pulse generator, where the charge lookup table is configured to provide a charge duration. The voltage converter includes a discharge lookup table coupled to the pulse generator, where the discharge lookup table is configured to provide a discharge duration. The voltage converter also includes a latch coupled to the charge lookup table, where the latch is configured to store an indication of a supply voltage.

公开(公告)号：US20240183885A1

公开(公告)日：2024-06-06

申请号：US18438754

申请日：2024-02-12

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Aravindhan Karuppiah

IPC: G01R19/10 ,  G01R19/165 ,  G01R19/25

CPC classification number: G01R19/10 ,  G01R19/16576 ,  G01R19/2506

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

公开(公告)号：US11933823B1

公开(公告)日：2024-03-19

申请号：US17962139

申请日：2022-10-07

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G ,  Aravindhan Karuppiah

IPC: G01R19/10 ,  G01R19/165 ,  G01R19/25

CPC classification number: G01R19/10 ,  G01R19/16576 ,  G01R19/2506

Abstract: An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.

公开(公告)号：US20240045761A1

公开(公告)日：2024-02-08

申请号：US18381320

申请日：2023-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F11/10 ,  G06F13/28

CPC classification number: G06F11/1004 ,  G06F13/28

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

公开(公告)号：US11829238B2

公开(公告)日：2023-11-28

申请号：US17378570

申请日：2021-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F11/10 ,  G06F11/00 ,  G06F13/28

CPC classification number: G06F11/1004 ,  G06F13/28

Abstract: In an example, a method includes copying data between a source device and a destination device to form first copied data. The method also includes, responsive to completion of the copying, performing a verify-read operation. The verify-read operation includes determining a first checksum of the first copied data, copying the data between the source device and the destination device to form second copied data, determining a second checksum of the second copied data, comparing the first checksum to the second checksum to determine a comparison result, and determining a data integrity validation result based on the comparison result.

公开(公告)号：US20230185679A1

公开(公告)日：2023-06-15

申请号：US18166787

申请日：2023-02-09

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan RAJU ,  Anand Kumar G

IPC: G06F11/16 ,  G06F11/14 ,  G06F13/20 ,  G06F11/07

CPC classification number: G06F11/1616 ,  G06F11/1441 ,  G06F13/20 ,  G06F11/0757 ,  G06F11/0745 ,  G06F2201/805

Abstract: A circuit includes a primary register region and a primary shadow register; a secondary register region and a secondary shadow register; and a safety controller having multiple states. The safety controller transitions to a first write state when a first write signal to write a first value to the primary register region is detected, and copies the first value written to the primary register region to the primary shadow register; transitions to a second write state when a second write signal to write a second value to the secondary register region is detected within a set amount of time of detection of the first write signal, and in the second write state, copies the second value written to the secondary register region to the secondary shadow register; transitions to a compare state to receive a comparison signal indicating whether the first value is the same as the second value; and transitions to an update state when the first value is the same as the second value.

公开(公告)号：US20230132069A1

公开(公告)日：2023-04-27

申请号：US17710906

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Robin Osa Hoel ,  Anand Kumar G ,  Dhivya Ravichandran ,  Aniruddha Periyapatna Nagendra

IPC: H03M13/09 ,  G06F13/40 ,  H03M13/00

Abstract: A circuit with an interface, a transmit data register coupled to the interface, a storage device coupled to the transmit data register and including a plurality of storage locations, each storage location adapted to store a data unit, and a serial register coupled between the storage device and an output. The circuit also includes a CRC generation circuit having an input coupled between an output of the transmit data register and the storage device. The CRC generation circuit includes a first CRC generation block for providing a CRC in response to an X-bit data unit and an X-bit polynomial and a second CRC generation block with a collective X-bit input for providing a CRC in response to an X-bit data unit and a 2X-bit polynomial in a single clock cycle and a 2X-bit data unit and a 2X-bit polynomial in two clock cycles.

公开(公告)号：US20230113657A1

公开(公告)日：2023-04-13

申请号：US18079324

申请日：2022-12-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anand Kumar G

IPC: G06F1/14 ,  G06F1/3225 ,  G06F1/3237

Abstract: A circuit comprises a power controller, a real-time clock (RTC) sub-system, and a processing sub-system. The RTC sub-system includes an alarm register storing a predetermined time for a task, and provides an early warning countdown and a scheduled event signal. The processing sub-system includes a processor, a preemptive wakeup circuit, and a component coupled to the processor and configured to execute the task with the processor. The preemptive wakeup circuit comprises a selector logic circuit, a comparator, and a wakeup initiation circuit. The selector logic circuit receives latency values indicative of wakeup times for a clock generator and the component, and outputs a longest wakeup time to the comparator, which indicates when the early warning countdown and the longest wakeup time are equal. The wakeup initiation circuit generates a clock request and disables the sleep mode indicator. The power controller provides a clock signal and wakes the component.

公开(公告)号：US11606099B1

公开(公告)日：2023-03-14

申请号：US17482734

申请日：2021-09-23

Applicant: Texas Instruments Incorporated

Inventor： Veeramanikandan Raju ,  Anand Kumar G

IPC: H03M1/06

Abstract: An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.